From patchwork Thu Jun 13 18:57:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Paul A. Clarke" X-Patchwork-Id: 33110 X-Patchwork-Delegate: tuliom@linux.vnet.ibm.com Received: (qmail 118039 invoked by alias); 13 Jun 2019 18:57:44 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 118029 invoked by uid 89); 13 Jun 2019 18:57:44 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-23.6 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW autolearn=ham version=3.3.1 spammy=H*i:sk:1560452 X-HELO: mx0a-001b2d01.pphosted.com From: "Paul A. Clarke" To: libc-alpha@sourceware.org Cc: tuliom@ascii.art.br, fweimer@redhat.com, joseph@codesourcery.com Subject: [PATCH 1/2 v2] [powerpc] add 'volatile' to asm Date: Thu, 13 Jun 2019 13:57:20 -0500 Message-Id: <1560452241-11638-2-git-send-email-pc@us.ibm.com> In-Reply-To: <1560452241-11638-1-git-send-email-pc@us.ibm.com> References: <1560452241-11638-1-git-send-email-pc@us.ibm.com> From: "Paul A. Clarke" Add 'volatile' keyword to a few asm statements, to force the compiler to generate the instructions therein. Some instances were implicitly volatile, but adding keyword for consistency. 2019-06-13 Paul A. Clarke * sysdeps/powerpc/fpu/fenv_libc.h (relax_fenv_state): Add 'volatile'. * sysdeps/powerpc/fpu/fpu_control.h (__FPU_MFFS): Likewise. (__FPU_MFFSL): Likewise. (_FPU_SETCW): Likewise. v2: This fixes issues seen by Tulio in my earlier posted patch "[powerpc] fegetround: utilize faster method to get rounding mode" which was not committed. --- sysdeps/powerpc/fpu/fenv_libc.h | 4 ++-- sysdeps/powerpc/fpu_control.h | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h index f8dd1b7..f66bf24 100644 --- a/sysdeps/powerpc/fpu/fenv_libc.h +++ b/sysdeps/powerpc/fpu/fenv_libc.h @@ -56,9 +56,9 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden; #define relax_fenv_state() \ do { \ if (GLRO(dl_hwcap) & PPC_FEATURE_HAS_DFP) \ - asm (".machine push; .machine \"power6\"; " \ + asm volatile (".machine push; .machine \"power6\"; " \ "mtfsfi 7,0,1; .machine pop"); \ - asm ("mtfsfi 7,0"); \ + asm volatile ("mtfsfi 7,0"); \ } while(0) /* Set/clear a particular FPSCR bit (for instance, diff --git a/sysdeps/powerpc/fpu_control.h b/sysdeps/powerpc/fpu_control.h index 07ccc84..0ab9331 100644 --- a/sysdeps/powerpc/fpu_control.h +++ b/sysdeps/powerpc/fpu_control.h @@ -67,7 +67,7 @@ typedef unsigned int fpu_control_t; /* Macros for accessing the hardware control word. */ # define __FPU_MFFS() \ ({register double __fr; \ - __asm__ ("mffs %0" : "=f" (__fr)); \ + __asm__ __volatile__("mffs %0" : "=f" (__fr)); \ __fr; \ }) @@ -81,7 +81,7 @@ typedef unsigned int fpu_control_t; #ifdef _ARCH_PWR9 # define __FPU_MFFSL() \ ({register double __fr; \ - __asm__ ("mffsl %0" : "=f" (__fr)); \ + __asm__ __volatile__("mffsl %0" : "=f" (__fr)); \ __fr; \ }) #else @@ -101,7 +101,7 @@ typedef unsigned int fpu_control_t; __u.__ll = 0xfff80000LL << 32; /* This is a QNaN. */ \ __u.__ll |= (cw) & 0xffffffffLL; \ __fr = __u.__d; \ - __asm__ ("mtfsf 255,%0" : : "f" (__fr)); \ + __asm__ __volatile__("mtfsf 255,%0" : : "f" (__fr)); \ } /* Default control word set at startup. */