From patchwork Thu Oct 30 21:07:00 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Torvald Riegel X-Patchwork-Id: 3505 Received: (qmail 588 invoked by alias); 30 Oct 2014 21:07:10 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 429 invoked by uid 89); 30 Oct 2014 21:07:07 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.4 required=5.0 tests=AWL, BAYES_00, RP_MATCHES_RCVD, SPF_HELO_PASS, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mx1.redhat.com Subject: [PATCH][RFC] Fix SPARC atomic_write_barrier. From: Torvald Riegel To: GLIBC Devel Cc: David Miller Date: Thu, 30 Oct 2014 22:07:00 +0100 Message-ID: <1414703220.10085.209.camel@triegel.csb> Mime-Version: 1.0 This patch changes SPARC write barriers to be just release barriers. I haven't tested this, so this is based on my understanding of the SPARC memory model (TSO). For a release barrier, we have code like foo = 1; atomic_write_barrier (); release_flag = 1; and release_flag could also be a spinlock unlock, for example. So we want to prevent store/store and load/store reordering, so that the release_flag assigment is the "last" thing. Previously, the write barriers prevented -- AFAIU SPARC assembly -- store/load reordering, which is what you'd need a full barrier for on TSO (e.g., consider Dekker synchronization). The other kinds of reordering barriers (e.g., load/store) are implicit on TSO (as on x86). Thus, the change doesn't fix a correctness issue (at least if using TSO!) but just a performance issue. Could someone who cares about SPARC please review and test this? commit 5adee7234e1ca9ea7b8998a096c369cddeea47c8 Author: Torvald Riegel Date: Wed Oct 29 19:14:14 2014 +0100 Fix SPARC atomic_write_barrier. diff --git a/sysdeps/sparc/sparc32/bits/atomic.h b/sysdeps/sparc/sparc32/bits/atomic.h index 1b4175d..2ae2eaa 100644 --- a/sysdeps/sparc/sparc32/bits/atomic.h +++ b/sysdeps/sparc/sparc32/bits/atomic.h @@ -346,8 +346,8 @@ extern uint64_t _dl_hwcap __attribute__((weak)); #define atomic_write_barrier() \ do { \ if (__atomic_is_v9) \ - /* membar #StoreLoad | #StoreStore */ \ - __asm __volatile (".word 0x8143e00a" : : : "memory"); \ + /* membar #LoadStore | #StoreStore */ \ + __asm __volatile (".word 0x8143e00c" : : : "memory"); \ else \ __asm __volatile ("" : : : "memory"); \ } while (0) diff --git a/sysdeps/sparc/sparc32/sparcv9/bits/atomic.h b/sysdeps/sparc/sparc32/sparcv9/bits/atomic.h index 8441de3..7644796 100644 --- a/sysdeps/sparc/sparc32/sparcv9/bits/atomic.h +++ b/sysdeps/sparc/sparc32/sparcv9/bits/atomic.h @@ -99,4 +99,4 @@ typedef uintmax_t uatomic_max_t; #define atomic_read_barrier() \ __asm __volatile ("membar #LoadLoad | #LoadStore" : : : "memory") #define atomic_write_barrier() \ - __asm __volatile ("membar #StoreLoad | #StoreStore" : : : "memory") + __asm __volatile ("membar #LoadStore | #StoreStore" : : : "memory") diff --git a/sysdeps/sparc/sparc64/bits/atomic.h b/sysdeps/sparc/sparc64/bits/atomic.h index ccb7319..2bca42b 100644 --- a/sysdeps/sparc/sparc64/bits/atomic.h +++ b/sysdeps/sparc/sparc64/bits/atomic.h @@ -120,4 +120,4 @@ typedef uintmax_t uatomic_max_t; #define atomic_read_barrier() \ __asm __volatile ("membar #LoadLoad | #LoadStore" : : : "memory") #define atomic_write_barrier() \ - __asm __volatile ("membar #StoreLoad | #StoreStore" : : : "memory") + __asm __volatile ("membar #LoadStore | #StoreStore" : : : "memory")