From patchwork Tue Oct 21 19:48:20 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Torvald Riegel X-Patchwork-Id: 3311 Received: (qmail 2288 invoked by alias); 21 Oct 2014 19:48:25 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 2278 invoked by uid 89); 21 Oct 2014 19:48:24 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.8 required=5.0 tests=AWL, BAYES_00, RP_MATCHES_RCVD, SPF_HELO_PASS autolearn=ham version=3.3.2 X-HELO: mx1.redhat.com Subject: [RFC][PATCH] powerpc: Change atomic_write_barrier to have release semantics. From: Torvald Riegel To: libc-alpha@sourceware.org Date: Tue, 21 Oct 2014 21:48:20 +0200 Message-ID: <1413920900.8483.59.camel@triegel.csb> Mime-Version: 1.0 Based on my scan of existing code, atomic_write_barrier is used as if it were a C11 memory_order_release fence. However, powerpc uses "eieio" currently, which, AFAIK, prohibits reordering of *only* stores. "lwsync" is used as release fence in other parts of the implementation (e.g., _rel versions of atomic ops), and it is a valid implementation of C11 memory_order_release fences. Therefore, this patch changes atomic_write_barrier to use "lwsync" when available, or "sync" otherwise. I have NOT tested this. Can somebody who cares about powerpc please have a look and test? Thanks! commit 07653467236190973356ae6a0cfd8cdf329a3d9c Author: Torvald Riegel Date: Sat Oct 18 01:01:58 2014 +0200 powerpc: Change atomic_write_barrier to have release semantics. diff --git a/sysdeps/powerpc/bits/atomic.h b/sysdeps/powerpc/bits/atomic.h index b838631..4fc0c5a 100644 --- a/sysdeps/powerpc/bits/atomic.h +++ b/sysdeps/powerpc/bits/atomic.h @@ -77,7 +77,6 @@ typedef uintmax_t uatomic_max_t; #endif #define atomic_full_barrier() __asm ("sync" ::: "memory") -#define atomic_write_barrier() __asm ("eieio" ::: "memory") #define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \ ({ \ diff --git a/sysdeps/powerpc/powerpc32/bits/atomic.h b/sysdeps/powerpc/powerpc32/bits/atomic.h index 7613bdc..a3dd09c 100644 --- a/sysdeps/powerpc/powerpc32/bits/atomic.h +++ b/sysdeps/powerpc/powerpc32/bits/atomic.h @@ -117,6 +117,7 @@ # ifndef UP # define __ARCH_REL_INSTR "lwsync" # endif +# define atomic_write_barrier() __asm ("lwsync" ::: "memory") #else /* * Older powerpc32 processors don't support the new "light weight" @@ -124,6 +125,7 @@ * for all powerpc32 applications. */ # define atomic_read_barrier() __asm ("sync" ::: "memory") +# define atomic_write_barrier() __asm ("sync" ::: "memory") #endif /* diff --git a/sysdeps/powerpc/powerpc64/bits/atomic.h b/sysdeps/powerpc/powerpc64/bits/atomic.h index 527fe7c..ed26b72 100644 --- a/sysdeps/powerpc/powerpc64/bits/atomic.h +++ b/sysdeps/powerpc/powerpc64/bits/atomic.h @@ -234,6 +234,7 @@ #ifndef UP # define __ARCH_REL_INSTR "lwsync" #endif +#define atomic_write_barrier() __asm ("lwsync" ::: "memory") /* * Include the rest of the atomic ops macros which are common to both