From patchwork Fri May 23 17:30:54 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wilco Dijkstra X-Patchwork-Id: 1106 Return-Path: X-Original-To: siddhesh@wilcox.dreamhost.com Delivered-To: siddhesh@wilcox.dreamhost.com Received: from homiemail-mx21.g.dreamhost.com (peon2454.g.dreamhost.com [208.113.200.127]) by wilcox.dreamhost.com (Postfix) with ESMTP id 79C48360098 for ; Fri, 23 May 2014 10:31:15 -0700 (PDT) Received: by homiemail-mx21.g.dreamhost.com (Postfix, from userid 14307373) id 230261896D20; Fri, 23 May 2014 10:31:14 -0700 (PDT) X-Original-To: glibc@patchwork.siddhesh.in Delivered-To: x14307373@homiemail-mx21.g.dreamhost.com Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by homiemail-mx21.g.dreamhost.com (Postfix) with ESMTPS id 8C80918C0CA3 for ; Fri, 23 May 2014 10:31:14 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:subject:date:message-id:mime-version :content-type; q=dns; s=default; b=r4xsfok8cWOdvBuDApPj9gwerEV81 fdDNLejjDKR49EiVL0EnXIixUXFQpXyh8q3eIt7ov6Yeqg2N836HG02uXQyczcx4 rkWsxKO1Q8GufJ1qWfbUckijcNjr+7cwj0UA8Hr4HHV3fAZoGtfHxxkNp3aEvUXI yj+j2xlzYhysTU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:subject:date:message-id:mime-version :content-type; s=default; bh=NHNFwJMoAv9PlWXCSSPiBU9Tt4s=; b=Rgw YC2PjJGPjqvexDfOfoaFLaUgP0gCSpl6BbIgSQiitDkJM+o9N+Rgj1PH8ARtMt1D OTNR2W92DGecoyGpGPQwYYYY4mQ2euouIN285h/BFw6xhElYs9vgifQClXBaUguf W4BBweodEMSJOGCuM4MA7IhctVXWc0a/OKavA25M= Received: (qmail 32587 invoked by alias); 23 May 2014 17:31:07 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 32532 invoked by uid 89); 23 May 2014 17:31:07 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.3 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com From: "Wilco" To: Subject: [PATCH] ARM: Avoid unnecessary FPSCR writes Date: Fri, 23 May 2014 18:30:54 +0100 Message-ID: <001d01cf76ac$c0676dd0$41364970$@com> MIME-Version: 1.0 X-MC-Unique: 114052318305900201 X-DH-Original-To: glibc@patchwork.siddhesh.in Hi, This patch speeds up the ARM fenv implementation by avoiding unnecessary FPSCR writes if the FPSCR remains unchanged. OK for commit? Wilco ChangeLog: 2014-05-23 Wilco * sysdeps/arm/fclrexcpt.c (feclearexcept): Optimize to avoid unnecessary FPSCR writes. * sysdeps/arm/fedisblxcpt.c (fedisableexcept): Likewise. * sysdeps/arm/feenablxcpt.c (feenableexcept): Likewise. * sysdeps/arm/fsetexcptflg.c (fesetexceptflag): Likewise. * sysdeps/arm/setfpucw.c (__setfpucw): Likewise. --- sysdeps/arm/fclrexcpt.c | 10 +++++----- sysdeps/arm/fedisblxcpt.c | 4 +++- sysdeps/arm/feenablxcpt.c | 14 +++++++------- sysdeps/arm/fsetexcptflg.c | 13 ++++++++----- sysdeps/arm/setfpucw.c | 11 ++++++----- 5 files changed, 29 insertions(+), 23 deletions(-) diff --git a/sysdeps/arm/fclrexcpt.c b/sysdeps/arm/fclrexcpt.c index cbf61a6..31420ed 100644 --- a/sysdeps/arm/fclrexcpt.c +++ b/sysdeps/arm/fclrexcpt.c @@ -24,7 +24,7 @@ int feclearexcept (int excepts) { - fpu_control_t fpscr; + fpu_control_t fpscr, new_fpscr; /* Fail if a VFP unit isn't present unless nothing needs to be done. */ if (!ARM_HAVE_VFP) @@ -32,11 +32,11 @@ feclearexcept (int excepts) _FPU_GETCW (fpscr); excepts &= FE_ALL_EXCEPT; + new_fpscr = fpscr & ~excepts; - /* Clear the relevant bits. */ - fpscr = (fpscr & ~FE_ALL_EXCEPT) | (fpscr & FE_ALL_EXCEPT & ~excepts); - - _FPU_SETCW (fpscr); + /* Write new exception flags if changed. */ + if (new_fpscr != fpscr) + _FPU_SETCW (new_fpscr); return 0; } diff --git a/sysdeps/arm/fedisblxcpt.c b/sysdeps/arm/fedisblxcpt.c index f2956cd..d5e0f00 100644 --- a/sysdeps/arm/fedisblxcpt.c +++ b/sysdeps/arm/fedisblxcpt.c @@ -35,7 +35,9 @@ fedisableexcept (int excepts) excepts &= FE_ALL_EXCEPT; new_fpscr = fpscr & ~(excepts << FE_EXCEPT_SHIFT); - _FPU_SETCW (new_fpscr); + /* Write new exceptions if changed. */ + if (new_fpscr != fpscr) + _FPU_SETCW (new_fpscr); return (fpscr >> FE_EXCEPT_SHIFT) & FE_ALL_EXCEPT; } diff --git a/sysdeps/arm/feenablxcpt.c b/sysdeps/arm/feenablxcpt.c index afd8943..f54ca6e 100644 --- a/sysdeps/arm/feenablxcpt.c +++ b/sysdeps/arm/feenablxcpt.c @@ -25,7 +25,7 @@ int feenableexcept (int excepts) { - fpu_control_t fpscr, new_fpscr; + fpu_control_t fpscr, new_fpscr, updated_fpscr; /* Fail if a VFP unit isn't present. */ if (!ARM_HAVE_VFP) @@ -35,15 +35,15 @@ feenableexcept (int excepts) excepts &= FE_ALL_EXCEPT; new_fpscr = fpscr | (excepts << FE_EXCEPT_SHIFT); - _FPU_SETCW (new_fpscr); - - if (excepts != 0) + if (new_fpscr != fpscr) { + _FPU_SETCW (new_fpscr); + /* Not all VFP architectures support trapping exceptions, so test whether the relevant bits were set and fail if not. */ - _FPU_GETCW (new_fpscr); - if ((new_fpscr & (excepts << FE_EXCEPT_SHIFT)) - != (excepts << FE_EXCEPT_SHIFT)) + _FPU_GETCW (updated_fpscr); + + if (new_fpscr & ~updated_fpscr) return -1; } diff --git a/sysdeps/arm/fsetexcptflg.c b/sysdeps/arm/fsetexcptflg.c index 1a610ff..28810d3 100644 --- a/sysdeps/arm/fsetexcptflg.c +++ b/sysdeps/arm/fsetexcptflg.c @@ -25,19 +25,22 @@ int fesetexceptflag (const fexcept_t *flagp, int excepts) { - fpu_control_t fpscr; + fpu_control_t fpscr, new_fpscr; /* Fail if a VFP unit isn't present unless nothing needs to be done. */ if (!ARM_HAVE_VFP) return (excepts != 0); _FPU_GETCW (fpscr); + excepts &= FE_ALL_EXCEPT; /* Set the desired exception mask. */ - fpscr &= ~(excepts & FE_ALL_EXCEPT); - fpscr |= (*flagp & excepts & FE_ALL_EXCEPT); + new_fpscr = fpscr & ~excepts; + new_fpscr |= *flagp & excepts; + + /* Write new exception flags if changed. */ + if (new_fpscr != fpscr) + _FPU_SETCW (new_fpscr); - /* Save state back to the FPU. */ - _FPU_SETCW (fpscr); return 0; } diff --git a/sysdeps/arm/setfpucw.c b/sysdeps/arm/setfpucw.c index 7416377..259b020 100644 --- a/sysdeps/arm/setfpucw.c +++ b/sysdeps/arm/setfpucw.c @@ -24,19 +24,20 @@ void __setfpucw (fpu_control_t set) { - fpu_control_t fpscr; + fpu_control_t fpscr, new_fpscr; /* Do nothing if a VFP unit isn't present. */ if (!ARM_HAVE_VFP) return; - /* Fetch the current control word. */ _FPU_GETCW (fpscr); /* Preserve the reserved bits, and set the rest as the user specified (or the default, if the user gave zero). */ - fpscr &= _FPU_RESERVED; - fpscr |= set & ~_FPU_RESERVED; + new_fpscr = fpscr & _FPU_RESERVED; + new_fpscr |= set & ~_FPU_RESERVED; - _FPU_SETCW (fpscr); + /* Write FPSCR if changed. */ + if (new_fpscr != fpscr) + _FPU_SETCW (fpscr); }