From patchwork Thu Oct 23 17:36:30 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wilco Dijkstra X-Patchwork-Id: 3350 Received: (qmail 5212 invoked by alias); 23 Oct 2014 17:36:36 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 5164 invoked by uid 89); 23 Oct 2014 17:36:35 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com From: "Wilco Dijkstra" To: Subject: [PATCH 13/13] AArch64: Cleanup fenv implementation Date: Thu, 23 Oct 2014 18:36:30 +0100 Message-ID: <001701cfeee7$e1d0fe60$a572fb20$@com> MIME-Version: 1.0 X-MC-Unique: 114102318363111401 Improve feenableexcept performance - avoid an unnecessary FPCR read in case the FPCR does not change. Also improve the logic of the return value. ChangeLog: 2014-10-23 Wilco Dijkstra * sysdeps/aarch64/fpu/feenablxcpt.c (feenableexcept): Optimize to avoid an unnecessary FPCR read. --- sysdeps/aarch64/fpu/feenablxcpt.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/sysdeps/aarch64/fpu/feenablxcpt.c b/sysdeps/aarch64/fpu/feenablxcpt.c index 763248f..dfb4120 100644 --- a/sysdeps/aarch64/fpu/feenablxcpt.c +++ b/sysdeps/aarch64/fpu/feenablxcpt.c @@ -24,24 +24,22 @@ feenableexcept (int excepts) { fpu_control_t fpcr; fpu_control_t fpcr_new; + fpu_control_t updated_fpcr; _FPU_GETCW (fpcr); excepts &= FE_ALL_EXCEPT; fpcr_new = fpcr | (excepts << FE_EXCEPT_SHIFT); if (fpcr != fpcr_new) - _FPU_SETCW (fpcr_new); - - /* Trapping exceptions are optional in AArch64 the relevant enable - bits in FPCR are RES0 hence the absence of support can be - detected by reading back the FPCR and comparing with the required - value. */ - if (excepts) { - fpu_control_t updated_fpcr; + _FPU_SETCW (fpcr_new); + /* Trapping exceptions are optional in AArch64; the relevant enable + bits in FPCR are RES0 hence the absence of support can be detected + by reading back the FPCR and comparing with the required value. */ _FPU_GETCW (updated_fpcr); - if (((updated_fpcr >> FE_EXCEPT_SHIFT) & excepts) != excepts) + + if (fpcr_new & ~updated_fpcr) return -1; }