From patchwork Thu Oct 23 17:36:18 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wilco Dijkstra X-Patchwork-Id: 3349 Received: (qmail 4473 invoked by alias); 23 Oct 2014 17:36:25 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 4312 invoked by uid 89); 23 Oct 2014 17:36:23 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com From: "Wilco Dijkstra" To: Subject: [PATCH 12/13] AArch64: Cleanup fenv implementation Date: Thu, 23 Oct 2014 18:36:18 +0100 Message-ID: <001601cfeee7$da6bd5f0$8f4381d0$@com> MIME-Version: 1.0 X-MC-Unique: 114102318361902301 Improve fesetenv performance by avoiding unnecessary FPSR/FPCR reads/writes. It uses the same logic as the ARM version. The common case removes 1 FPSR and 1 FPCR read. For FE_DFL_ENV and FE_NOMASK_ENV a FPCR read is avoided in case the FPCR does not change. ChangeLog: 2014-10-23 Wilco Dijkstra * sysdeps/aarch64/fpu/fesetenv.c (fesetenv): Optimize to reduce FPCR/FPSR accesses. --- sysdeps/aarch64/fpu/fesetenv.c | 40 +++++++++++++++++++++++----------------- 1 file changed, 23 insertions(+), 17 deletions(-) diff --git a/sysdeps/aarch64/fpu/fesetenv.c b/sysdeps/aarch64/fpu/fesetenv.c index c19680d..f71014d 100644 --- a/sysdeps/aarch64/fpu/fesetenv.c +++ b/sysdeps/aarch64/fpu/fesetenv.c @@ -29,8 +29,20 @@ fesetenv (const fenv_t *envp) fpu_fpsr_t fpsr_new; _FPU_GETCW (fpcr); - _FPU_GETFPSR (fpsr); + if ((envp != FE_DFL_ENV) && (envp != FE_NOMASK_ENV)) + { + /* The new FPCR/FPSR are valid, so don't merge the reserved flags. */ + fpcr_new = envp->__fpcr; + + if (fpcr != fpcr_new) + _FPU_SETCW (fpcr_new); + + _FPU_SETFPSR (envp->__fpsr); + return 0; + } + + _FPU_GETFPSR (fpsr); fpcr_new = fpcr & _FPU_RESERVED; fpsr_new = fpsr & _FPU_FPSR_RESERVED; @@ -39,31 +51,25 @@ fesetenv (const fenv_t *envp) fpcr_new |= _FPU_DEFAULT; fpsr_new |= _FPU_FPSR_DEFAULT; } - else if (envp == FE_NOMASK_ENV) + else { fpcr_new |= _FPU_FPCR_IEEE; fpsr_new |= _FPU_FPSR_IEEE; } - else - { - fpcr_new |= envp->__fpcr & ~_FPU_RESERVED; - fpsr_new |= envp->__fpsr & ~_FPU_FPSR_RESERVED; - } - if (fpsr != fpsr_new) - _FPU_SETFPSR (fpsr_new); + _FPU_SETFPSR (fpsr_new); if (fpcr != fpcr_new) - _FPU_SETCW (fpcr_new); + { + _FPU_SETCW (fpcr_new); - /* Trapping exceptions are optional in AArch64 the relevant enable - bits in FPCR are RES0 hence the absence of support can be - detected by reading back the FPCR and comparing with the required - value. */ + /* Trapping exceptions are optional in AArch64; the relevant enable + bits in FPCR are RES0 hence the absence of support can be detected + by reading back the FPCR and comparing with the required value. */ + _FPU_GETCW (updated_fpcr); - _FPU_GETCW (updated_fpcr); - if ((updated_fpcr & fpcr_new) != fpcr_new) - return 1; + return fpcr_new & ~updated_fpcr; + } return 0; }