| Message ID | 20250221095740.582183-1-daichengrong@iscas.ac.cn (mailing list archive) |
|---|---|
| Headers |
Return-Path: <libc-alpha-bounces~patchwork=sourceware.org@sourceware.org> X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E44AC3858410 for <patchwork@sourceware.org>; Fri, 21 Feb 2025 09:58:36 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E44AC3858410 X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from cstnet.cn (smtp81.cstnet.cn [159.226.251.81]) by sourceware.org (Postfix) with ESMTPS id 3ADAE3858C42 for <libc-alpha@sourceware.org>; Fri, 21 Feb 2025 09:57:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3ADAE3858C42 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 3ADAE3858C42 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=159.226.251.81 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1740131872; cv=none; b=TCqz0RnYlsMggNO+2UNIB5Yfq68FfxeGuCTYkUOgMO1Jb2Vgn17Z4eS9aflCXINYI4xatFXUmd1+EdBalaMwFAEaEg3KbQqnFqbIuLqGqPRWMz9//DYj+Kq49/LGJZSHQMqodHTxfkwfqOOsdVPfgNTzIZQnRH7L/OJ7cLfhA78= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1740131872; c=relaxed/simple; bh=8FJdHLsqnSFXUUTmftj+zlaSsio6iDhA7l7h8MAFcrU=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=NpIBLk5B/bfzcmoMpCgqb20xL0cBPuXi308ydW8gwTuvesYx/zM0jX8Oajg6OoIszh6DH2S+cgSjnDxKGBwmdaMylgc8GksNvCNzXn0BDUP2k/yu1VK0VIiqemJileGrtNRDJr431UTZaBsoAlMWVDt3nM3Mn7bt6UOY97xMX14= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3ADAE3858C42 Received: from chengrong-ubuntu-02.home.arpa (unknown [124.16.138.129]) by APP-03 (Coremail) with SMTP id rQCowAAX_jAVTrhnrXEdDw--.13464S2; Fri, 21 Feb 2025 17:57:41 +0800 (CST) From: daichengrong@iscas.ac.cn To: libc-alpha@sourceware.org Cc: aswaterman@gmail.com, palmer@rivosinc.com, adhemerval.zanella@linaro.org, darius@bluespec.com, jiageng08@iscas.ac.cn, enh@google.com Subject: [PATCH v7 0/2] RISC-V: add multiarch RVV support for memcpy using FMV IFUNC Date: Fri, 21 Feb 2025 17:57:38 +0800 Message-Id: <20250221095740.582183-1-daichengrong@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID: rQCowAAX_jAVTrhnrXEdDw--.13464S2 X-Coremail-Antispam: 1UD129KBjvdXoWrtrWfJw48CFyfGw1rKw15Jwb_yoWDGrb_Cr 4Ivry8Z3y8XF48JFZrGrs8Kry7urWrJr92qF9rtr1jgr47Gr1jganrt345X3WUXFWDXw4f Jws3Ar18Kry2yjkaLaAFLSUrUUUUbb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUIcSsGvfJTRUUUba8YjsxI4VWDJwAYFVCjjxCrM7AC8VAFwI0_Gr0_Xr1l1xkIjI8I 6I8E6xAIw20EY4v20xvaj40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l8cAvFVAK0II2c7xJM2 8CjxkF64kEwVA0rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVWDJVCq3wA2z4x0Y4vE2Ix0 cI8IcVCY1x0267AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwV C2z280aVCY1x0267AKxVW0oVCq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC 0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUtVWrXwAv7VC2z280aVAFwI0_Gr1j6F 4UJwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41lw4CEc2x0rVAKj4xxMxkF 7I0En4kS14v26r126r1DMxkIecxEwVAFwVW8uwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4 IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1r MI8E67AF67kF1VAFwI0_JF0_Jw1lIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJV WUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr1lIxAIcVCF04k26cxKx2IYs7xG6r1j 6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Jr0_GrUvcS sGvfC2KfnxnUUI43ZEXa7IU8_hLUUUUUU== X-Originating-IP: [124.16.138.129] X-CM-SenderInfo: pgdluxxhqj201qj6x2xfdvhtffof0/ X-Spam-Status: No, score=-6.7 required=5.0 tests=BAYES_00, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list <libc-alpha.sourceware.org> List-Unsubscribe: <https://sourceware.org/mailman/options/libc-alpha>, <mailto:libc-alpha-request@sourceware.org?subject=unsubscribe> List-Archive: <https://sourceware.org/pipermail/libc-alpha/> List-Post: <mailto:libc-alpha@sourceware.org> List-Help: <mailto:libc-alpha-request@sourceware.org?subject=help> List-Subscribe: <https://sourceware.org/mailman/listinfo/libc-alpha>, <mailto:libc-alpha-request@sourceware.org?subject=subscribe> Errors-To: libc-alpha-bounces~patchwork=sourceware.org@sourceware.org |
| Series |
RISC-V: add multiarch RVV support for memcpy using FMV IFUNC
|
|
Message
daichengrong
Feb. 21, 2025, 9:57 a.m. UTC
From: daichengrong <daichengrong@iscas.ac.cn>
Change in v7:
update dl_hwcap support using kernel header
update rvv memcpy compile with option,+v
delete optimization for small lengths
This patch introduces vector support for memcpy with IFUNC.
The implementation selects the RVV optimized memcpy version via dl_hwcap.
daichengrong (2):
check rvv support in asm at sysdeps/riscv
add riscv vector support for memcpy
config.h.in | 3 ++
sysdeps/riscv/configure | 35 ++++++++++++++++++
sysdeps/riscv/configure.ac | 25 +++++++++++++
sysdeps/riscv/multiarch/memcpy_vector.S | 37 +++++++++++++++++++
.../unix/sysv/linux/riscv/multiarch/Makefile | 6 +++
.../linux/riscv/multiarch/ifunc-impl-list.c | 14 +++++++
.../unix/sysv/linux/riscv/multiarch/memcpy.c | 8 ++++
7 files changed, 128 insertions(+)
mode change 100644 => 100755 sysdeps/riscv/configure
create mode 100644 sysdeps/riscv/multiarch/memcpy_vector.S
Comments
在 2025/2/21 17:57:38, daichengrong@iscas.ac.cn 写道: > From: daichengrong <daichengrong@iscas.ac.cn> > > Change in v7: > update dl_hwcap support using kernel header > update rvv memcpy compile with option,+v > delete optimization for small lengths > > This patch introduces vector support for memcpy with IFUNC. > The implementation selects the RVV optimized memcpy version via dl_hwcap. > > daichengrong (2): > check rvv support in asm at sysdeps/riscv > add riscv vector support for memcpy > > config.h.in | 3 ++ > sysdeps/riscv/configure | 35 ++++++++++++++++++ > sysdeps/riscv/configure.ac | 25 +++++++++++++ > sysdeps/riscv/multiarch/memcpy_vector.S | 37 +++++++++++++++++++ > .../unix/sysv/linux/riscv/multiarch/Makefile | 6 +++ > .../linux/riscv/multiarch/ifunc-impl-list.c | 14 +++++++ > .../unix/sysv/linux/riscv/multiarch/memcpy.c | 8 ++++ > 7 files changed, 128 insertions(+) > mode change 100644 => 100755 sysdeps/riscv/configure > create mode 100644 sysdeps/riscv/multiarch/memcpy_vector.S I Recently noticed the Patch Queue Review meeting, and as mentioned in the previous notes, I am confused about the mean of RISCV maintainers are working on this. Does it mean that the RVV support provided by machine maintainers will come soon? Before that, any patches on RVV support will not be accepted?
On Tue, 2025-03-04 at 10:50 +0800, daichengrong wrote: > > 在 2025/2/21 17:57:38, daichengrong@iscas.ac.cn 写道: > > From: daichengrong <daichengrong@iscas.ac.cn> > > > > Change in v7: > > update dl_hwcap support using kernel header > > update rvv memcpy compile with option,+v > > delete optimization for small lengths > > > > This patch introduces vector support for memcpy with IFUNC. > > The implementation selects the RVV optimized memcpy version via > > dl_hwcap. > > > > daichengrong (2): > > check rvv support in asm at sysdeps/riscv > > add riscv vector support for memcpy > > > > config.h.in | 3 ++ > > sysdeps/riscv/configure | 35 > > ++++++++++++++++++ > > sysdeps/riscv/configure.ac | 25 +++++++++++++ > > sysdeps/riscv/multiarch/memcpy_vector.S | 37 > > +++++++++++++++++++ > > .../unix/sysv/linux/riscv/multiarch/Makefile | 6 +++ > > .../linux/riscv/multiarch/ifunc-impl-list.c | 14 +++++++ > > .../unix/sysv/linux/riscv/multiarch/memcpy.c | 8 ++++ > > 7 files changed, 128 insertions(+) > > mode change 100644 => 100755 sysdeps/riscv/configure > > create mode 100644 sysdeps/riscv/multiarch/memcpy_vector.S > I Recently noticed the Patch Queue Review meeting, and as mentioned in > the previous notes, I am confused about the mean of RISCV maintainers > are working on this. Does it mean that the RVV support provided by > machine maintainers will come soon? Before that, any patches on RVV > support will not be accepted? No, it means the RISC-V maintainers should review this patch.