From patchwork Fri Apr 21 07:54:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hau Hsu X-Patchwork-Id: 55709 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 69FB0385B52E for ; Fri, 21 Apr 2023 07:54:45 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 69FB0385B52E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1682063685; bh=dU3ZfBILGbcTuaZ4aQIBgpURESHYlTet9LMlgxgVsqI=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=mBBoqG5QoDN19eYPvJM64iRwG9jLPjX1uScmeObiBsg7FVZ5iUHnSa+SFQcn54TQ5 5Q9q2ukvQWwG/pQwR90wc9MIB/+Yrkb/HCk3W8fF4em2Qjv3duE2Z/Ory/KgFIOniR cv+m6HnCq/2dUWQVDA1qWHtC/HVzmNybyV/cXMQk= X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-pf1-x42b.google.com (mail-pf1-x42b.google.com [IPv6:2607:f8b0:4864:20::42b]) by sourceware.org (Postfix) with ESMTPS id 8527C3858C83 for ; Fri, 21 Apr 2023 07:54:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8527C3858C83 Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-63b4a64c72bso1667564b3a.0 for ; Fri, 21 Apr 2023 00:54:22 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682063661; x=1684655661; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=dU3ZfBILGbcTuaZ4aQIBgpURESHYlTet9LMlgxgVsqI=; b=RLyX+Mf3Pe6WcFv+jDN0fHyUawWcNjLBJEciIHIOvgl1Ih41FtK43B7GKvfXfEs980 Z2lCzupfMvtWgWfLqf7x2+cOrqHnTFHOXzHBlFURscuMhAUCceacKLf/ucr780yjY0AZ y35Kdjd4q9g+Mr1sfOuBngydHU2luk2bcM3ifaHHgT0+83VW2IrT/3ISkTAvxAtrSyu9 u5qClvvCUiuzKiS+JhkaeuY47A1Y2j5rLVeeJ26CIAUiIz0ONNt6HIDgVc18bUAiGjVL dKmWosGKBOQOvWMJTo684oxtM+c+Poz7HuSdM03nSGId3Xmc3m1B4ruvODajk+M7W3s8 mLNQ== X-Gm-Message-State: AAQBX9e9jxM+Oq3gf3iRQ+5mvhzRx+ZIab7tdtVRrpLhJxbHiY6c95e3 sjbWcksSHW22ph9jxl4PAqrskAZ6MOkybL3baYU0xFVOSMowza7WeNceSK6vFipAdlGQ5KWDxwC zUQdNxQoDeISJXEIFJ+VfRa58xQtbXBK8UhKi3Bqbf/frl0bvIrKnt69PTvy+AgigMfhCxdAYgc p8UxCu X-Google-Smtp-Source: AKy350ZRFwsp0B0n0zO1rw1BT3aGoyt9xtK/O95gK4Nz5yZz8MnoKx4zMOz7Ser9NdNgg2h3DRTJcw== X-Received: by 2002:a05:6a20:1582:b0:f0:5920:77b1 with SMTP id h2-20020a056a20158200b000f0592077b1mr6595782pzj.28.1682063661177; Fri, 21 Apr 2023 00:54:21 -0700 (PDT) Received: from localhost.localdomain (1-169-217-217.dynamic-ip.hinet.net. [1.169.217.217]) by smtp.gmail.com with ESMTPSA id fa23-20020a056a002d1700b006259e883ee9sm650992pfb.189.2023.04.21.00.54.19 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 21 Apr 2023 00:54:20 -0700 (PDT) To: libc-alpha@sourceware.org, hongrong.hsu@sifive.com, jerry.shih@sifive.com, nick.knight@sifive.com, kito.cheng@sifive.com Cc: greentime.hu@sifive.com, alice.chan@sifive.com, andrew@sifive.com, vincent.chen@sifive.com, hau.hsu@sifive.com Subject: [PATCH v2 0/5] riscv: Vectorized mem*/str* function Date: Fri, 21 Apr 2023 15:54:00 +0800 Message-Id: <20230421075405.14892-1-hau.hsu@sifive.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Hau Hsu via Libc-alpha From: Hau Hsu Reply-To: Hau Hsu Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org Sender: "Libc-alpha" I am submitting version 2 of the patch for adding vectorized mem*/str* functions for RISC-V. This patch builds upon the previous version (v1) available at https://patchwork.sourceware.org/project/glibc/list/?series=17710. In this version, we have included the __memcmpeq function and set lmul=1 for memcmp, which improves its generality. Jerry Shih (2): riscv: vectorized mem* functions riscv: vectorized str* functions Nick Knight (1): riscv: vectorized strchr and strnlen functions Vincent Chen (1): riscv: Enabling vectorized mem*/str* functions in build time Yun Hsiang (1): riscv: add vectorized __memcmpeq scripts/build-many-glibcs.py | 10 ++++ sysdeps/riscv/preconfigure | 19 +++++++ sysdeps/riscv/preconfigure.ac | 18 +++++++ sysdeps/riscv/rv32/rvv/Implies | 2 + sysdeps/riscv/rv64/rvv/Implies | 2 + sysdeps/riscv/rvv/memchr.S | 63 +++++++++++++++++++++++ sysdeps/riscv/rvv/memcmp.S | 71 ++++++++++++++++++++++++++ sysdeps/riscv/rvv/memcmpeq.S | 69 +++++++++++++++++++++++++ sysdeps/riscv/rvv/memcpy.S | 51 +++++++++++++++++++ sysdeps/riscv/rvv/memmove.S | 72 ++++++++++++++++++++++++++ sysdeps/riscv/rvv/memset.S | 51 +++++++++++++++++++ sysdeps/riscv/rvv/strcat.S | 72 ++++++++++++++++++++++++++ sysdeps/riscv/rvv/strchr.S | 53 +++++++++++++++++++ sysdeps/riscv/rvv/strcmp.S | 93 ++++++++++++++++++++++++++++++++++ sysdeps/riscv/rvv/strcpy.S | 56 ++++++++++++++++++++ sysdeps/riscv/rvv/strlen.S | 54 ++++++++++++++++++++ sysdeps/riscv/rvv/strncat.S | 83 ++++++++++++++++++++++++++++++ sysdeps/riscv/rvv/strncmp.S | 85 +++++++++++++++++++++++++++++++ sysdeps/riscv/rvv/strncpy.S | 86 +++++++++++++++++++++++++++++++ sysdeps/riscv/rvv/strnlen.S | 56 ++++++++++++++++++++ 20 files changed, 1066 insertions(+) create mode 100644 sysdeps/riscv/rv32/rvv/Implies create mode 100644 sysdeps/riscv/rv64/rvv/Implies create mode 100644 sysdeps/riscv/rvv/memchr.S create mode 100644 sysdeps/riscv/rvv/memcmp.S create mode 100644 sysdeps/riscv/rvv/memcmpeq.S create mode 100644 sysdeps/riscv/rvv/memcpy.S create mode 100644 sysdeps/riscv/rvv/memmove.S create mode 100644 sysdeps/riscv/rvv/memset.S create mode 100644 sysdeps/riscv/rvv/strcat.S create mode 100644 sysdeps/riscv/rvv/strchr.S create mode 100644 sysdeps/riscv/rvv/strcmp.S create mode 100644 sysdeps/riscv/rvv/strcpy.S create mode 100644 sysdeps/riscv/rvv/strlen.S create mode 100644 sysdeps/riscv/rvv/strncat.S create mode 100644 sysdeps/riscv/rvv/strncmp.S create mode 100644 sysdeps/riscv/rvv/strncpy.S create mode 100644 sysdeps/riscv/rvv/strnlen.S