From patchwork Mon Oct 3 19:59:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 55167 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 817BD3841889 for ; Mon, 3 Oct 2022 20:00:54 +0000 (GMT) X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) by sourceware.org (Postfix) with ESMTPS id AA0083856948 for ; Mon, 3 Oct 2022 19:59:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org AA0083856948 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=aurel32.net Authentication-Results: sourceware.org; spf=none smtp.mailfrom=aurel32.net DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=Content-Transfer-Encoding:MIME-Version:Message-Id:Date: Subject:Cc:To:From:Content-Type:From:Reply-To:Subject:Content-ID: Content-Description:In-Reply-To:References:X-Debbugs-Cc; bh=CM/MBvdxJzb0kqPFumn9ljrr4xGfae0OzfIjhpEbvYQ=; b=x2ozo0NZPSqoD44ILioVn+oD++ 8qd4mFlu/GVfe9h1+CD0nS0qgt73mOSoA9y+roT6LOuPNVbRPX5fEyJ3EtePq8waL2cBcXZUkYm/a t0Z+ewcJZ/a25/klEQSYWnVb/hMSOMyOIgZBg8J2eIetxZqEnUSVD8eMX9rswJdZFJQ7pHQbOKWNM NwixGbqLlrTD2LxHz+4GFYpHzXRZtUcdhTIKn019VhyU2QgMCdVShBpDxK/fSlCIIi4l4b7X1Or9G 1BtwPlbOy910U5RggecL2cUAvkAflg1U4Nw7CsdkojgYspMS3oXZt8WZ0KwvlZA1wJiDUgg/iJG7e F/s+8cFA==; Received: from [2a01:e34:ec5d:a741:8a4c:7c4e:dc4c:1787] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1ofRbS-00GHJ8-M3; Mon, 03 Oct 2022 21:59:50 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.96) (envelope-from ) id 1ofRbP-00DjwE-1X; Mon, 03 Oct 2022 21:59:47 +0200 From: Aurelien Jarno To: libc-alpha@sourceware.org Subject: [PATCH v3 0/8] x86: Fix AVX2 string functions requiring BMI1, BMI2 or LZCNT (BZ #29611) Date: Mon, 3 Oct 2022 21:59:36 +0200 Message-Id: <20221003195944.3274548-1-aurelien@aurel32.net> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 X-Spam-Status: No, score=-7.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, SPF_HELO_PASS, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aurelien Jarno Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org Sender: "Libc-alpha" Some early Intel Haswell CPU have AVX2 instructions, but do not have BMI1 and BMI2 instructions. Some AVX2 string functions only check for AVX2, but use BMI1, BMI2 or LZCNT instructions. This patchset tries to fix that. While most fixes only change ifunc-impl-list.c, and thus only concerns the testsuite, the changes to str*cmp and wcs(n)cmp are a real issue affecting early Intel Haswell CPU, reported to affect Debian Sid and Fedora Rawhide. On the other hand, the check for LZCNT in memrchr is purely for correctness, I am not aware of a CPU implementing AVX2 without LZCNT. This has been tested by remplacing all BMI1 and BMI2 instructions in the source code by the "ud2" instruction and disabling the BMI1, BMI2 feature detection, and running the testsuite. Resolves: BZ #29611 Changes v2 -> v3: - Change the way patches are split. No code change. Change v1 -> v2: - Better scan for BMI2 instructions (shlx and shrx) and BMI1 instructions (blsmsk) instructions following the feedback from Noah Goldstein Aurelien Jarno (8): x86: include BMI1 and BMI2 in x86-64-v3 level x86-64: Require BMI2 for AVX2 str(n)casecmp implementations x86-64: Require BMI2 for AVX2 strcmp implementation x86-64: Require BMI2 for AVX2 strncmp implementation x86-64: Require BMI2 for AVX2 wcs(n)cmp implementations x86-64: Require BMI2 for AVX2 (raw|w)memchr implementations x86-64: Require BMI2 and LZCNT for AVX2 memrchr implementation x86-64: Require BMI1/BMI2 for AVX2 strrchr and wcsrchr implementations sysdeps/x86/get-isa-level.h | 2 + sysdeps/x86/isa-level.h | 2 + sysdeps/x86_64/multiarch/ifunc-avx2.h | 2 + sysdeps/x86_64/multiarch/ifunc-impl-list.c | 86 ++++++++++++++++----- sysdeps/x86_64/multiarch/ifunc-strcasecmp.h | 1 + sysdeps/x86_64/multiarch/strcmp.c | 4 +- sysdeps/x86_64/multiarch/strncmp.c | 4 +- 7 files changed, 76 insertions(+), 25 deletions(-) Reviewed-by: Noah Goldstein