Message ID | 20220118043159.27521-1-vincent.chen@sifive.com |
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Return-Path: <libc-alpha-bounces+patchwork=sourceware.org@sourceware.org> X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CF4FC3857C49 for <patchwork@sourceware.org>; Tue, 18 Jan 2022 04:32:25 +0000 (GMT) X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-pl1-x633.google.com (mail-pl1-x633.google.com [IPv6:2607:f8b0:4864:20::633]) by sourceware.org (Postfix) with ESMTPS id 3D9623858406 for <libc-alpha@sourceware.org>; Tue, 18 Jan 2022 04:32:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 3D9623858406 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-pl1-x633.google.com with SMTP id e19so23232738plc.10 for <libc-alpha@sourceware.org>; Mon, 17 Jan 2022 20:32:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id; bh=oAzqY5e+jKik50QtJEjpyRBIJQsQHCQd/BGg4ThKTiw=; b=a64xoW+os4kV8S7tjdXxXb/xadjYdT4nK0n+vlVWGwxqAm9kRsf6uQyfIfco27tmNX SLz48V4Vz0qTrOY+resrFs5LUzLM0Dk3i6k18E++Y8rs+Aiy0DLIUwODhI2KSWfNR2YF T3S2MVyyf1KuThl3Y683LExO4aOOfcb4y0fOSaCkpkgJ/fewo7kM6CQPMXqs9soTY/sP un24ZQQ85/x4WiOpzm6pcIBW3v7ebSALjnPD5rEAO4RzXa1G63Z020WFr3PLSjO1d8k+ uoA8UuS7AuJ+CORmxTWQ2qYanr7eK/1efFblRaBeMqrTDNVl0VzKzzcdZ+bKy5ueh5GV PBPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=oAzqY5e+jKik50QtJEjpyRBIJQsQHCQd/BGg4ThKTiw=; b=P2DNsgm6tIqPftn0xOeyZrNx7Mc5vr3EONDxAp8KolFi7k641mAC2jWCyILNB3hEG9 5RZPuqtsJJeMgvubW+POK17M97l71q9MfFtTwsYbkEktSuCdnQdW0a3pgyTWB5BROEEU CO4h/1dLiDafknL4vhx4E7i7qoF6Mq21R4vo+NhKqhzBhG8z6lJjZ43lClR4v5uQBWOb XhRzTevxVmstCSBiJzT8ckYAqPmIrIZGES9vkVlC6bde0qppYAhX8owqSLstpucBieGw g2l3Yd3+X9fDKsPWZdfxLyE/hERY0o/fvA8BUEUNmY12FnlZeb/2tEvjesNiWp2tQ25J bpjQ== X-Gm-Message-State: AOAM533UBtGmE2M6hfpTjRsn2JLs+xbUCooSiAATgxZYLKZYsIXV6pF5 Z6JYCGMJtSflqCujNQICnZC2Cmq17SPGOw== X-Google-Smtp-Source: ABdhPJyg+0MwJLxGElwVqrrM9P5uBlU5Qun82o3CZF9IEk7NC7r5XEdQArahuxt+w9RU8gbCUOQ+gg== X-Received: by 2002:a17:90b:3845:: with SMTP id nl5mr18989127pjb.116.1642480332211; Mon, 17 Jan 2022 20:32:12 -0800 (PST) Received: from VincentChen-ThinkPad-T480s.internal.sifive.com (36-226-198-98.dynamic-ip.hinet.net. [36.226.198.98]) by smtp.gmail.com with ESMTPSA id y69sm15646861pfg.171.2022.01.17.20.32.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jan 2022 20:32:11 -0800 (PST) From: Vincent Chen <vincent.chen@sifive.com> To: libc-alpha@sourceware.org, palmer@dabbelt.com, darius@bluespec.com, andrew@sifive.com, dj@redhat.com Subject: [PATCH v2 0/2] RISC-V: Add vector ISA support Date: Tue, 18 Jan 2022 12:31:57 +0800 Message-Id: <20220118043159.27521-1-vincent.chen@sifive.com> X-Mailer: git-send-email 2.17.1 X-Spam-Status: No, score=-5.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list <libc-alpha.sourceware.org> List-Unsubscribe: <https://sourceware.org/mailman/options/libc-alpha>, <mailto:libc-alpha-request@sourceware.org?subject=unsubscribe> List-Archive: <https://sourceware.org/pipermail/libc-alpha/> List-Post: <mailto:libc-alpha@sourceware.org> List-Help: <mailto:libc-alpha-request@sourceware.org?subject=help> List-Subscribe: <https://sourceware.org/mailman/listinfo/libc-alpha>, <mailto:libc-alpha-request@sourceware.org?subject=subscribe> Cc: greentime.hu@sifive.com, kito.cheng@sifive.com, Vincent Chen <vincent.chen@sifive.com> Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org Sender: "Libc-alpha" <libc-alpha-bounces+patchwork=sourceware.org@sourceware.org> |
Series |
RISC-V: Add vector ISA support
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Message
Vincent Chen
Jan. 18, 2022, 4:31 a.m. UTC
According to the feedback for the version 1 patch set, only the "RISC-V: Remove riscv-specific sigcontext.h" patch remains in this version patch set. It means that MINSIGSTKSZ, SIGSTKSZ, and PTHREAD_STACK_MIN are not changed after introducing the V-extension support. Therefore, the current definition of the above stack size is insufficient to backup all vector registers. In this circumstance, users have to use the mechanisms submitted by H.J. Lu https://sourceware.org/git/?p=glibc.git;a=commit;h=6c57d320484988e87e446e2e60ce42816bf51d53 and https://sourceware.org/git/?p=glibc.git;a=commit;h=5d98a7dae955bafa6740c26eaba9c86060ae0344 to obtain the appropriate size of the current system setting. Besides, a new calling convention using vector registers to transfer argument or return value probably be proposed in the feature. It may cause the resolved functions and audit functions to corrupt the content of the vector registers, which are used as argument registers and address return registers. To avoid this problem, this patch set includes Hsiangkai Wang's patch to enable the Glibc dynamic loader to directly resolve the function symbols whose calling convention is incompatible with the standard calling convention. The corresponding implementation in Binutils can be found in https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8155b8539b55bca87378129e02009cd8907d8c8c. Hsiangkai Wang (1): riscv: Resolve symbols directly for symbols with STO_RISCV_VARIANT_CC. Vincent Chen (1): RISC-V: remove riscv-specific sigcontext.h elf/elf.h | 7 +++++ manual/platform.texi | 6 +++++ .../sigcontext.h => riscv/dl-dtprocnum.h} | 22 +++++----------- sysdeps/riscv/dl-machine.h | 26 +++++++++++++++++++ 4 files changed, 45 insertions(+), 16 deletions(-) rename sysdeps/{unix/sysv/linux/riscv/bits/sigcontext.h => riscv/dl-dtprocnum.h} (55%)