From patchwork Fri Jun 20 06:09:41 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajit Kumar Agarwal X-Patchwork-Id: 1586 Received: (qmail 18938 invoked by alias); 20 Jun 2014 06:10:04 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 18925 invoked by uid 89); 20 Jun 2014 06:10:02 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_HELO_PASS, SPF_PASS autolearn=ham version=3.3.2 X-HELO: na01-bl2-obe.outbound.protection.outlook.com Received: from mail-bl2lp0203.outbound.protection.outlook.com (HELO na01-bl2-obe.outbound.protection.outlook.com) (207.46.163.203) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Fri, 20 Jun 2014 06:10:00 +0000 Received: from BY2FFO11FD052.protection.gbl (10.1.14.32) by BY2FFO11HUB041.protection.gbl (10.1.14.82) with Microsoft SMTP Server (TLS) id 15.0.969.12; Fri, 20 Jun 2014 06:09:44 +0000 Received: from xsj-pvapsmtpgw01 (149.199.60.83) by BY2FFO11FD052.mail.protection.outlook.com (10.1.15.189) with Microsoft SMTP Server (TLS) id 15.0.969.12 via Frontend Transport; Fri, 20 Jun 2014 06:09:44 +0000 Received: from unknown-38-66.xilinx.com ([149.199.38.66] helo=xsj-smtp1) by xsj-pvapsmtpgw01 with esmtp (Exim 4.63) (envelope-from ) id 1Wxs1I-0002F8-Fw; Thu, 19 Jun 2014 23:09:52 -0700 From: Ajit Kumar Agarwal To: "gdb-patches@sourceware.org" CC: Michael Eager , Pedro Alves , Vinod Kathail , Vidhumouli Hunsigida , Nagaraju Mekala Subject: RE: [Patch, microblaze]: Add support of microblaze software single stepping Date: Fri, 20 Jun 2014 06:09:41 +0000 MIME-Version: 1.0 X-RCIS-Action: ALLOW Message-ID: X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.83; CTRY:US; IPV:NLI; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(6009001)(438001)(189002)(199002)(377424004)(53416004)(50466002)(31696002)(64706001)(47776003)(79102001)(92726001)(76482001)(87936001)(83072002)(2656002)(85852003)(99396002)(46406003)(97756001)(92566001)(86362001)(20776003)(77982001)(21056001)(46102001)(54356999)(50986999)(81342001)(19580395003)(83322001)(19580405001)(6806004)(44976005)(74502001)(74662001)(31966008)(1496007)(80022001)(85306003)(23726002)(95666004)(104016002)(74316001)(77096002)(81542001)(70736001)(33646001)(4396001); DIR:OUT; SFP:; SCL:1; SRVR:BY2FFO11HUB041; H:xsj-pvapsmtpgw01; FPR:; MLV:sfv; PTR:unknown-60-83.xilinx.com; MX:1; A:1; LANG:en; X-OriginatorOrg: xilinx.onmicrosoft.com X-Microsoft-Antispam: BCL:0;PCL:0;RULEID: X-Forefront-PRVS: 024847EE92 Received-SPF: Pass (: domain of xilinx.com designates 149.199.60.83 as permitted sender) receiver=; client-ip=149.199.60.83; helo=xsj-pvapsmtpgw01; Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=ajit.kumar.agarwal@xilinx.com; Please find the patch that supports the microblaze software single stepping. This patch handles the cases of branch and return with delay slot and the imm instruction in microblaze. Could you please review and let me know if its okay. [Patch, microblaze]: Add support of microblaze software single stepping This patch adds the support of microblaze software single stepping. It handles the cases of branch and return with delay slot and imm instruction in microblaze. ChangeLog: 2014-06-19 Ajit Agarwal * microblaze-tdep.c (microblaze_software_single_step): New. (microblaze_gdbarch_init): Use of set_gdbarch_software_single_step. Signed-off-by:Ajit Agarwal ajitkum@xilinx.com --- gdb/microblaze-tdep.c | 79 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 79 insertions(+), 0 deletions(-) diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c index 14c1b52..3de2f70 100644 --- a/gdb/microblaze-tdep.c +++ b/gdb/microblaze-tdep.c @@ -628,6 +628,83 @@ microblaze_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) return (TYPE_LENGTH (type) == 16); } +static int +microblaze_software_single_step (struct frame_info *frame) +{ + struct gdbarch *arch = get_frame_arch (frame); + struct address_space *aspace = get_frame_address_space (frame); + struct gdbarch_tdep *tdep = gdbarch_tdep (arch); + enum bfd_endian byte_order = gdbarch_byte_order (arch); + int ret = 0; + int ii; + CORE_ADDR pc; + long insn; + enum microblaze_instr minstr; + bfd_boolean isunsignednum; + enum microblaze_instr_type insn_type; + short delay_slots; + int imm; + bfd_boolean immfound = FALSE; + CORE_ADDR breaks[2] = {-1,-1}; + CORE_ADDR address; + int targetvalid; + + /* Set a breakpoint at the next instruction */ + /* If the current instruction is an imm, set it at the inst after */ + /* If the instruction has a delay slot, skip the delay slot */ + pc = get_frame_pc (frame); + insn = microblaze_fetch_instruction (pc); + minstr = get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots); + if (insn_type == immediate_inst) + { + int rd, ra, rb; + immfound = TRUE; + minstr = microblaze_decode_insn (insn, &rd, &ra, &rb, &imm); + pc = pc + INST_WORD_SIZE; + insn = microblaze_fetch_instruction (pc); + minstr = get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots); + } + if (insn_type != return_inst) + breaks[0] = pc + delay_slots * INST_WORD_SIZE + INST_WORD_SIZE; + + /* Now check for branch or return instructions */ + if (insn_type == branch_inst || insn_type == return_inst) + { + int limm; + int lrd, lra, lrb; + int ra, rb; + bfd_boolean targetvalid; + bfd_boolean unconditionalbranch; + microblaze_decode_insn (insn, &lrd, &lra, &lrb, &limm); + if (lra >= 0 && lra < MICROBLAZE_NUM_REGS) + ra = get_frame_register_unsigned (frame, lra); + else + ra = 0; + if (lrb >= 0 && lrb < MICROBLAZE_NUM_REGS) + rb = get_frame_register_unsigned (frame, lrb); + else + rb = 0; + address = microblaze_get_target_address (insn, immfound, imm, pc, ra, rb, &targetvalid, &unconditionalbranch); + + if (!unconditionalbranch) + breaks[1] = address; + } + + /* Insert the breakpoints */ + if (breaks[0] != -1) + { + insert_single_step_breakpoint (arch, aspace, breaks[0]); + ret = 1; + } + if (breaks[1] != -1) + { + insert_single_step_breakpoint (arch, aspace, breaks[1]); + ret = 1; + } + + return ret; +} + static void microblaze_write_pc (struct regcache *regcache, CORE_ADDR pc) { @@ -708,6 +785,8 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) set_gdbarch_breakpoint_from_pc (gdbarch, microblaze_breakpoint_from_pc); + set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step); + set_gdbarch_frame_args_skip (gdbarch, 8); set_gdbarch_print_insn (gdbarch, print_insn_microblaze);