From patchwork Wed Aug 29 16:40:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Burgess X-Patchwork-Id: 29107 Received: (qmail 124333 invoked by alias); 29 Aug 2018 16:41:16 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 124236 invoked by uid 89); 29 Aug 2018 16:41:15 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.1 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=OTHER X-HELO: mail-wm0-f43.google.com Received: from mail-wm0-f43.google.com (HELO mail-wm0-f43.google.com) (74.125.82.43) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 29 Aug 2018 16:41:14 +0000 Received: by mail-wm0-f43.google.com with SMTP id m199-v6so4938117wma.1 for ; Wed, 29 Aug 2018 09:41:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=t9/XLVoSgy/PxVi2eCL8thwdcx+B3pWwwrhY+E2Xmdo=; b=bI6stntk6KStqHT8pT4DUaeGRVah2DpTMNsxXzNthme0zEERXF9HluFrDhVsi0wNSU yJ5gPl5yD5SFrOzQPGsu4fu/Ofp5acdamCaCNhb4C76dak0BiiqMVFSwQWhbkoTzGbWE n+7gOTalQtIF2ftvtgMvqSZjoxRNZsplmlqexOsIzOQxHjz7jpakK5NIWvvJu/gWSyZS /dD4ZuFR8GzPGOEf0KmHjc+t71qdm7yiDkE2o3qTvMBiF7vuXQY0+fgM0fi20pulbDfd TRC3xiAaHfeu+LYUyBCvD+9OkfUT9jWMGGMKqqXtgj7RqRn3hsq2OUDdEnTwXrU0peLk 3sZg== Return-Path: Received: from localhost (host86-134-20-86.range86-134.btcentralplus.com. [86.134.20.86]) by smtp.gmail.com with ESMTPSA id j20-v6sm2775103wmh.9.2018.08.29.09.41.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 29 Aug 2018 09:41:10 -0700 (PDT) From: Andrew Burgess To: gdb-patches@sourceware.org Cc: jimw@sifive.com, palmer@sifive.com, Andrew Burgess Subject: [PATCH 2/4] gdb/riscv: Extend instruction decode to cover more instructions Date: Wed, 29 Aug 2018 17:40:52 +0100 Message-Id: In-Reply-To: References: In-Reply-To: References: X-IsSubscribed: yes Extends the instruction decoder used during prologue scan and software single step to cover more instructions. These instructions are encountered when running the current GDB testsuite with the DWARF stack unwinders turned off. gdb/ChangeLog: * riscv-tdep.c (riscv_insn::decode): Decode c.addi4spn, c.sd, c.sw, c.swsp, and c.sdsp. --- gdb/ChangeLog | 5 +++++ gdb/riscv-tdep.c | 40 ++++++++++++++++++++++++++++++++++++++-- 2 files changed, 43 insertions(+), 2 deletions(-) diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index 2f619c35e75..b4ac83a6dd9 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -972,6 +972,31 @@ private: m_imm.s = EXTRACT_STYPE_IMM (ival); } + /* Helper for DECODE, decode 16-bit CS-type instruction. The immediate + encoding is different for each CSS format instruction, so extracting + the immediate is left up to the caller, who should pass the extracted + immediate value through in IMM. */ + void decode_cs_type_insn (enum opcode opcode, ULONGEST ival, int imm) + { + m_opcode = opcode; + m_imm.s = imm; + m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S); + m_rs2 = decode_register_index_short (ival, OP_SH_CRS2S); + } + + /* Helper for DECODE, decode 16-bit CSS-type instruction. The immediate + encoding is different for each CSS format instruction, so extracting + the immediate is left up to the caller, who should pass the extracted + immediate value through in IMM. */ + void decode_css_type_insn (enum opcode opcode, ULONGEST ival, int imm) + { + m_opcode = opcode; + m_imm.s = imm; + m_rs1 = RISCV_SP_REGNUM; + /* Not a compressed register number in this case. */ + m_rs2 = decode_register_index (ival, OP_SH_CRS2); + } + /* Helper for DECODE, decode 32-bit U-type instruction. */ void decode_u_type_insn (enum opcode opcode, ULONGEST ival) { @@ -1165,14 +1190,25 @@ riscv_insn::decode (struct gdbarch *gdbarch, CORE_ADDR pc) m_rd = m_rs1 = decode_register_index (ival, OP_SH_RD); m_imm.s = EXTRACT_RVC_ADDI16SP_IMM (ival); } + else if (xlen < 16 && is_c_addi4spn_insn (ival)) + { + m_opcode = ADDI; + m_rd = decode_register_index_short (ival, OP_SH_CRS2S); + m_rs1 = RISCV_SP_REGNUM; + m_imm.s = EXTRACT_RVC_ADDI4SPN_IMM (ival); + } else if (is_c_lui_insn (ival)) m_opcode = OTHER; /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only, and C_FSW is RV32 only. */ else if (xlen != 4 && is_c_sd_insn (ival)) - m_opcode = OTHER; + decode_cs_type_insn (SD, ival, EXTRACT_RVC_LD_IMM (ival)); else if (is_c_sw_insn (ival)) - m_opcode = OTHER; + decode_cs_type_insn (SW, ival, EXTRACT_RVC_LW_IMM (ival)); + else if (is_c_swsp_insn (ival)) + decode_css_type_insn (SW, ival, EXTRACT_RVC_SWSP_IMM (ival)); + else if (is_c_sdsp_insn (ival)) + decode_css_type_insn (SW, ival, EXTRACT_RVC_SDSP_IMM (ival)); /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR. So must try to match C_JR first as it ahs more bits in mask. */ else if (is_c_jr_insn (ival))