[23/40] sim/m32r: Add explicit casts

Message ID d2faa21ffb9c02c8cf765920d3a993a2dcca31a1.1666258361.git.research_trasio@irq.a4lg.com
State Committed
Headers
Series sim+gdb: Suppress warnings if built with Clang (big batch 1) |

Commit Message

Tsukasa OI Oct. 20, 2022, 9:32 a.m. UTC
  Clang generates a warning if there is an enum value with a mismatching type
without an explicit cast ("-Wenum-conversion").
On the default configuration, it causes a build failure
(unless "--disable-werror" is specified).

This commit adds explicit casts on the M32R instruction decoder.

Note:
This commit touches CGEN-generated files directly.
Modifying CGEN is the best way to prevent this issue from happening again
but there is another known regression in CGEN or sim/m32r to resolve.
---
 sim/m32r/decode.c  | 14 +++++++-------
 sim/m32r/decode2.c | 14 +++++++-------
 sim/m32r/decodex.c | 14 +++++++-------
 3 files changed, 21 insertions(+), 21 deletions(-)
  

Comments

Mike Frysinger Oct. 23, 2022, 2:57 p.m. UTC | #1
On 20 Oct 2022 09:32, Tsukasa OI wrote:
> Clang generates a warning if there is an enum value with a mismatching type
> without an explicit cast ("-Wenum-conversion").
> On the default configuration, it causes a build failure
> (unless "--disable-werror" is specified).
> 
> This commit adds explicit casts on the M32R instruction decoder.
> 
> Note:
> This commit touches CGEN-generated files directly.
> Modifying CGEN is the best way to prevent this issue from happening again
> but there is another known regression in CGEN or sim/m32r to resolve.

same feedback as what i posted to "[PATCH 14/40] sim/frv: Add explicit casts"
-mike
  

Patch

diff --git a/sim/m32r/decode.c b/sim/m32r/decode.c
index 4b4b9f922e2..8066425c0d6 100644
--- a/sim/m32r/decode.c
+++ b/sim/m32r/decode.c
@@ -39,12 +39,12 @@  static IDESC m32rbf_insn_data[M32RBF_INSN__MAX];
 
 static const struct insn_sem m32rbf_insn_sem[] =
 {
-  { VIRTUAL_INSN_X_INVALID, M32RBF_INSN_X_INVALID, M32RBF_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_AFTER, M32RBF_INSN_X_AFTER, M32RBF_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_BEFORE, M32RBF_INSN_X_BEFORE, M32RBF_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_CTI_CHAIN, M32RBF_INSN_X_CTI_CHAIN, M32RBF_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_CHAIN, M32RBF_INSN_X_CHAIN, M32RBF_SFMT_EMPTY },
-  { VIRTUAL_INSN_X_BEGIN, M32RBF_INSN_X_BEGIN, M32RBF_SFMT_EMPTY },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_INVALID, M32RBF_INSN_X_INVALID, M32RBF_SFMT_EMPTY },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_AFTER, M32RBF_INSN_X_AFTER, M32RBF_SFMT_EMPTY },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_BEFORE, M32RBF_INSN_X_BEFORE, M32RBF_SFMT_EMPTY },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_CTI_CHAIN, M32RBF_INSN_X_CTI_CHAIN, M32RBF_SFMT_EMPTY },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_CHAIN, M32RBF_INSN_X_CHAIN, M32RBF_SFMT_EMPTY },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_BEGIN, M32RBF_INSN_X_BEGIN, M32RBF_SFMT_EMPTY },
   { M32R_INSN_ADD, M32RBF_INSN_ADD, M32RBF_SFMT_ADD },
   { M32R_INSN_ADD3, M32RBF_INSN_ADD3, M32RBF_SFMT_ADD3 },
   { M32R_INSN_AND, M32RBF_INSN_AND, M32RBF_SFMT_ADD },
@@ -153,7 +153,7 @@  static const struct insn_sem m32rbf_insn_sem[] =
 
 static const struct insn_sem m32rbf_insn_sem_invalid =
 {
-  VIRTUAL_INSN_X_INVALID, M32RBF_INSN_X_INVALID, M32RBF_SFMT_EMPTY
+  (CGEN_INSN_TYPE) VIRTUAL_INSN_X_INVALID, M32RBF_INSN_X_INVALID, M32RBF_SFMT_EMPTY
 };
 
 /* Initialize an IDESC from the compile-time computable parts.  */
diff --git a/sim/m32r/decode2.c b/sim/m32r/decode2.c
index 00b216b83fc..4833a3aa9ab 100644
--- a/sim/m32r/decode2.c
+++ b/sim/m32r/decode2.c
@@ -43,12 +43,12 @@  static IDESC m32r2f_insn_data[M32R2F_INSN__MAX];
 
 static const struct insn_sem m32r2f_insn_sem[] =
 {
-  { VIRTUAL_INSN_X_INVALID, M32R2F_INSN_X_INVALID, M32R2F_SFMT_EMPTY, NOPAR, NOPAR  },
-  { VIRTUAL_INSN_X_AFTER, M32R2F_INSN_X_AFTER, M32R2F_SFMT_EMPTY, NOPAR, NOPAR  },
-  { VIRTUAL_INSN_X_BEFORE, M32R2F_INSN_X_BEFORE, M32R2F_SFMT_EMPTY, NOPAR, NOPAR  },
-  { VIRTUAL_INSN_X_CTI_CHAIN, M32R2F_INSN_X_CTI_CHAIN, M32R2F_SFMT_EMPTY, NOPAR, NOPAR  },
-  { VIRTUAL_INSN_X_CHAIN, M32R2F_INSN_X_CHAIN, M32R2F_SFMT_EMPTY, NOPAR, NOPAR  },
-  { VIRTUAL_INSN_X_BEGIN, M32R2F_INSN_X_BEGIN, M32R2F_SFMT_EMPTY, NOPAR, NOPAR  },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_INVALID, M32R2F_INSN_X_INVALID, M32R2F_SFMT_EMPTY, NOPAR, NOPAR  },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_AFTER, M32R2F_INSN_X_AFTER, M32R2F_SFMT_EMPTY, NOPAR, NOPAR  },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_BEFORE, M32R2F_INSN_X_BEFORE, M32R2F_SFMT_EMPTY, NOPAR, NOPAR  },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_CTI_CHAIN, M32R2F_INSN_X_CTI_CHAIN, M32R2F_SFMT_EMPTY, NOPAR, NOPAR  },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_CHAIN, M32R2F_INSN_X_CHAIN, M32R2F_SFMT_EMPTY, NOPAR, NOPAR  },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_BEGIN, M32R2F_INSN_X_BEGIN, M32R2F_SFMT_EMPTY, NOPAR, NOPAR  },
   { M32R_INSN_ADD, M32R2F_INSN_ADD, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_ADD, M32R2F_INSN_WRITE_ADD },
   { M32R_INSN_ADD3, M32R2F_INSN_ADD3, M32R2F_SFMT_ADD3, NOPAR, NOPAR  },
   { M32R_INSN_AND, M32R2F_INSN_AND, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_AND, M32R2F_INSN_WRITE_AND },
@@ -186,7 +186,7 @@  static const struct insn_sem m32r2f_insn_sem[] =
 
 static const struct insn_sem m32r2f_insn_sem_invalid =
 {
-  VIRTUAL_INSN_X_INVALID, M32R2F_INSN_X_INVALID, M32R2F_SFMT_EMPTY, NOPAR, NOPAR
+  (CGEN_INSN_TYPE) VIRTUAL_INSN_X_INVALID, M32R2F_INSN_X_INVALID, M32R2F_SFMT_EMPTY, NOPAR, NOPAR
 };
 
 /* Initialize an IDESC from the compile-time computable parts.  */
diff --git a/sim/m32r/decodex.c b/sim/m32r/decodex.c
index 19bb1e5b8ff..4d77350b99a 100644
--- a/sim/m32r/decodex.c
+++ b/sim/m32r/decodex.c
@@ -43,12 +43,12 @@  static IDESC m32rxf_insn_data[M32RXF_INSN__MAX];
 
 static const struct insn_sem m32rxf_insn_sem[] =
 {
-  { VIRTUAL_INSN_X_INVALID, M32RXF_INSN_X_INVALID, M32RXF_SFMT_EMPTY, NOPAR, NOPAR  },
-  { VIRTUAL_INSN_X_AFTER, M32RXF_INSN_X_AFTER, M32RXF_SFMT_EMPTY, NOPAR, NOPAR  },
-  { VIRTUAL_INSN_X_BEFORE, M32RXF_INSN_X_BEFORE, M32RXF_SFMT_EMPTY, NOPAR, NOPAR  },
-  { VIRTUAL_INSN_X_CTI_CHAIN, M32RXF_INSN_X_CTI_CHAIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR  },
-  { VIRTUAL_INSN_X_CHAIN, M32RXF_INSN_X_CHAIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR  },
-  { VIRTUAL_INSN_X_BEGIN, M32RXF_INSN_X_BEGIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR  },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_INVALID, M32RXF_INSN_X_INVALID, M32RXF_SFMT_EMPTY, NOPAR, NOPAR  },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_AFTER, M32RXF_INSN_X_AFTER, M32RXF_SFMT_EMPTY, NOPAR, NOPAR  },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_BEFORE, M32RXF_INSN_X_BEFORE, M32RXF_SFMT_EMPTY, NOPAR, NOPAR  },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_CTI_CHAIN, M32RXF_INSN_X_CTI_CHAIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR  },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_CHAIN, M32RXF_INSN_X_CHAIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR  },
+  { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_BEGIN, M32RXF_INSN_X_BEGIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR  },
   { M32R_INSN_ADD, M32RXF_INSN_ADD, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_ADD, M32RXF_INSN_WRITE_ADD },
   { M32R_INSN_ADD3, M32RXF_INSN_ADD3, M32RXF_SFMT_ADD3, NOPAR, NOPAR  },
   { M32R_INSN_AND, M32RXF_INSN_AND, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_AND, M32RXF_INSN_WRITE_AND },
@@ -179,7 +179,7 @@  static const struct insn_sem m32rxf_insn_sem[] =
 
 static const struct insn_sem m32rxf_insn_sem_invalid =
 {
-  VIRTUAL_INSN_X_INVALID, M32RXF_INSN_X_INVALID, M32RXF_SFMT_EMPTY, NOPAR, NOPAR
+  (CGEN_INSN_TYPE) VIRTUAL_INSN_X_INVALID, M32RXF_INSN_X_INVALID, M32RXF_SFMT_EMPTY, NOPAR, NOPAR
 };
 
 /* Initialize an IDESC from the compile-time computable parts.  */