diff --git a/sim/m32r/m32r2.c b/sim/m32r/m32r2.c
index 9c8daa5b8c6..13c2990a6ab 100644
--- a/sim/m32r/m32r2.c
+++ b/sim/m32r/m32r2.c
@@ -26,6 +26,11 @@
#include "sim-main.h"
#include "cgen-mem.h"
#include "cgen-ops.h"
+#include "decode.h"
+
+/* From cpu.h. */
+extern CPUREG_FETCH_FN m32rbf_fetch_register;
+extern CPUREG_STORE_FN m32rbf_store_register;
/* The contents of BUF are in target byte order. */
diff --git a/sim/m32r/m32rx.c b/sim/m32r/m32rx.c
index 07098036d02..2fde1bb043f 100644
--- a/sim/m32r/m32rx.c
+++ b/sim/m32r/m32rx.c
@@ -26,6 +26,11 @@ along with this program. If not, see . */
#include "sim-main.h"
#include "cgen-mem.h"
#include "cgen-ops.h"
+#include "decode.h"
+
+/* From cpu.h. */
+extern CPUREG_FETCH_FN m32rbf_fetch_register;
+extern CPUREG_STORE_FN m32rbf_store_register;
/* The contents of BUF are in target byte order. */
diff --git a/sim/m32r/sim-if.c b/sim/m32r/sim-if.c
index 878a0d5f576..3530b8d711c 100644
--- a/sim/m32r/sim-if.c
+++ b/sim/m32r/sim-if.c
@@ -25,6 +25,7 @@
#include "sim/callback.h"
#include "sim-main.h"
+#include "sim-hw.h"
#include "sim-options.h"
#include "libiberty.h"
#include "bfd.h"
@@ -33,6 +34,9 @@
#define M32R_DEFAULT_MEM_SIZE 0x2000000 /* 32M */
+/* From cpu.h. */
+void m32rbf_h_cr_set (SIM_CPU *, UINT, USI);
+
static void free_state (SIM_DESC);
static void print_m32r_misc_cpu (SIM_CPU *cpu, int verbose);
diff --git a/sim/m32r/traps.c b/sim/m32r/traps.c
index 12a87b4a697..f0fb218a11d 100644
--- a/sim/m32r/traps.c
+++ b/sim/m32r/traps.c
@@ -55,6 +55,21 @@
#include
#endif
+/* From cpu.h, cpux.h and cpu2.h. */
+SI m32rbf_h_gr_get (SIM_CPU *, UINT);
+void m32rbf_h_gr_set (SIM_CPU *, UINT, SI);
+USI m32rbf_h_cr_get (SIM_CPU *, UINT);
+void m32rbf_h_cr_set (SIM_CPU *, UINT, USI);
+UQI m32rbf_h_psw_get (SIM_CPU *);
+void m32rbf_h_psw_set (SIM_CPU *, UQI);
+void m32rbf_h_bpsw_set (SIM_CPU *, UQI);
+UQI m32rxf_h_psw_get (SIM_CPU *);
+void m32rxf_h_psw_set (SIM_CPU *, UQI);
+void m32rxf_h_bpsw_set (SIM_CPU *, UQI);
+UQI m32r2f_h_psw_get (SIM_CPU *);
+void m32r2f_h_psw_set (SIM_CPU *, UQI);
+void m32r2f_h_bpsw_set (SIM_CPU *, UQI);
+
#define TRAP_LINUX_SYSCALL 2
#define TRAP_FLUSH_CACHE 12
/* The semantic code invokes this for invalid (unrecognized) instructions. */