From patchwork Thu Oct 20 09:32:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 59160 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0D336389EC5F for ; Thu, 20 Oct 2022 09:39:21 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 0D336389EC5F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1666258761; bh=2Jyojvpf0wDc6yfE/QUT7dFufCy6iFELlB0jSBeT5oc=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=PGlJikDjhE84uzEJFOgP8kFgmqN5ZEZ13i9C+6vqCIVUJ8OoVdCa74wgWgWXyIcUX rHTLjKVU5sLVBvLl4N8m9tEDdBbaTBROWWK3NkLB2bTY0/KuZe4dy21h+SomqboaKE 5GiVKDjN7JDbS12iuOt4IvY3HHCXpCFen/LjYIcQ= X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 07E9F382C7C7 for ; Thu, 20 Oct 2022 09:36:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 07E9F382C7C7 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 52FC5300089; Thu, 20 Oct 2022 09:36:24 +0000 (UTC) To: Tsukasa OI , Andrew Burgess , Mike Frysinger , Nick Clifton Subject: [PATCH 20/40] sim/m32r: Prepare required functions Date: Thu, 20 Oct 2022 09:32:25 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Gdb-patches From: Tsukasa OI Reply-To: Tsukasa OI Cc: gdb-patches@sourceware.org Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org Sender: "Gdb-patches" This commit includes necessary header files and creates duplicated declarations from other header files. Duplicated declarations are necessary on M32R because, despite that some m32rbf functions are used by m32rx and m32r2, we cannot include two or more CPU header files: "cpu.h", "cpux.h" and "cpu2.h". --- sim/m32r/m32r2.c | 5 +++++ sim/m32r/m32rx.c | 5 +++++ sim/m32r/sim-if.c | 4 ++++ sim/m32r/traps.c | 15 +++++++++++++++ 4 files changed, 29 insertions(+) diff --git a/sim/m32r/m32r2.c b/sim/m32r/m32r2.c index 9c8daa5b8c6..13c2990a6ab 100644 --- a/sim/m32r/m32r2.c +++ b/sim/m32r/m32r2.c @@ -26,6 +26,11 @@ #include "sim-main.h" #include "cgen-mem.h" #include "cgen-ops.h" +#include "decode.h" + +/* From cpu.h. */ +extern CPUREG_FETCH_FN m32rbf_fetch_register; +extern CPUREG_STORE_FN m32rbf_store_register; /* The contents of BUF are in target byte order. */ diff --git a/sim/m32r/m32rx.c b/sim/m32r/m32rx.c index 07098036d02..2fde1bb043f 100644 --- a/sim/m32r/m32rx.c +++ b/sim/m32r/m32rx.c @@ -26,6 +26,11 @@ along with this program. If not, see . */ #include "sim-main.h" #include "cgen-mem.h" #include "cgen-ops.h" +#include "decode.h" + +/* From cpu.h. */ +extern CPUREG_FETCH_FN m32rbf_fetch_register; +extern CPUREG_STORE_FN m32rbf_store_register; /* The contents of BUF are in target byte order. */ diff --git a/sim/m32r/sim-if.c b/sim/m32r/sim-if.c index 878a0d5f576..3530b8d711c 100644 --- a/sim/m32r/sim-if.c +++ b/sim/m32r/sim-if.c @@ -25,6 +25,7 @@ #include "sim/callback.h" #include "sim-main.h" +#include "sim-hw.h" #include "sim-options.h" #include "libiberty.h" #include "bfd.h" @@ -33,6 +34,9 @@ #define M32R_DEFAULT_MEM_SIZE 0x2000000 /* 32M */ +/* From cpu.h. */ +void m32rbf_h_cr_set (SIM_CPU *, UINT, USI); + static void free_state (SIM_DESC); static void print_m32r_misc_cpu (SIM_CPU *cpu, int verbose); diff --git a/sim/m32r/traps.c b/sim/m32r/traps.c index 12a87b4a697..f0fb218a11d 100644 --- a/sim/m32r/traps.c +++ b/sim/m32r/traps.c @@ -55,6 +55,21 @@ #include #endif +/* From cpu.h, cpux.h and cpu2.h. */ +SI m32rbf_h_gr_get (SIM_CPU *, UINT); +void m32rbf_h_gr_set (SIM_CPU *, UINT, SI); +USI m32rbf_h_cr_get (SIM_CPU *, UINT); +void m32rbf_h_cr_set (SIM_CPU *, UINT, USI); +UQI m32rbf_h_psw_get (SIM_CPU *); +void m32rbf_h_psw_set (SIM_CPU *, UQI); +void m32rbf_h_bpsw_set (SIM_CPU *, UQI); +UQI m32rxf_h_psw_get (SIM_CPU *); +void m32rxf_h_psw_set (SIM_CPU *, UQI); +void m32rxf_h_bpsw_set (SIM_CPU *, UQI); +UQI m32r2f_h_psw_get (SIM_CPU *); +void m32r2f_h_psw_set (SIM_CPU *, UQI); +void m32r2f_h_bpsw_set (SIM_CPU *, UQI); + #define TRAP_LINUX_SYSCALL 2 #define TRAP_FLUSH_CACHE 12 /* The semantic code invokes this for invalid (unrecognized) instructions. */