From patchwork Fri Feb 14 19:33:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Maciej W. Rozycki" X-Patchwork-Id: 38084 Received: (qmail 94941 invoked by alias); 14 Feb 2020 19:33:50 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 94919 invoked by uid 89); 14 Feb 2020 19:33:48 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-8.4 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, KAM_SHORT autolearn=ham version=3.3.1 spammy=sk:breakpo X-HELO: esa2.hgst.iphmx.com Received: from esa2.hgst.iphmx.com (HELO esa2.hgst.iphmx.com) (68.232.143.124) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 14 Feb 2020 19:33:45 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1581708871; x=1613244871; h=date:from:to:cc:subject:in-reply-to:message-id: references:mime-version; bh=A+2rVvoTvYo+1vUhH1PrWtnl9p4ac89VFpWgebUpnG8=; b=KHReoE70YcgCshN1UTM6GpEm74bfYZDJbK7vXomINOaPwNQi7tMjKF2+ aH5KzMowyzRfKJk1nwOED4MgUpxUA6ivA55XyjFR9fOPrezGzqHvXiltv 18JyA2WuQmzFo7prHnTgRF32ykMXwtsKoeXni5tfN7WPygukBH8Fuygrk f+Yqm5kKJwtlTixM2vyJQLN7XfppPPkbKm8X6BFjiKiLuvlHOiAdSlnRE K3QTndGrYJDvCwoDfkhRxuZMTdfMPu/qtG2Pt3ACWBoJFih5z5iK6YqXU 4G2FLfnDPJB7tiASKq203+Jl1ifUlYOM9smxKpA+ZB18zHuyZ1xmf1jl2 A==; IronPort-SDR: bjgW41cjSQtrgRes04YUENP31b32PHwnAlymqczzN3sT2bevjibhgBhgYYtuK/djljXyg1YpVh E108rQp5qmUbEczjEDA5PpaozMesKjwAq8FzVW9Nml+gv6Xs8PbwpKcI/Kd1Db4Au+J3mjSWSA Hw8xZN9vcVjEl9xUfqW220JfAyQo2hIUha94oaO1Th5IyKAQHc8HuR55AP8vURXZFsP+p82fbO DWBYPNiMfVG8TSyrl3NPkblvLMID//IPLlhVLCvg+7ck6bRDwApCkuZ50CU0ltiKgcg+QPPIIQ 3CY= X-URL-LookUp-ScanningError: 1 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 15 Feb 2020 03:34:04 +0800 IronPort-SDR: v/wUyfN++l6PyQjrRJ2kI4DUkAbL4BX4cZxkxHAHeK5TncdYUZwCkmPQs0xM1B3HoR0TsW/Rmy zo4+1B1iuOVTymBU/xCMjDa5NiMK+tK5ZxNtvTf2PrSnzYqqqHPZz5qgnwxlfdbocQaELlPE9u L+gsfGmc/6iGODpONozMKastsqA7Kbmw1zzBEn0P9rtevlM84EzZCncFUMbqDL9tf7XExumlXz 7xTg+1AaU8j6fY2vjMT6Zn2ZCTq98F7lk88DKChIRFeGv/TNmAy5uJRCU1vfPuvqyuEWVyt8L8 NXaX0X3+5kavrg1I1407kbpI Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Feb 2020 11:26:12 -0800 IronPort-SDR: 345NGiztTMSjR3l0+nLiAX79F88TzjS9FVxZNO7K2DEmFffITGYJZIZy12vegOtxdut1R7j5N5 s8M46GgciwMWWDcspIUHDCJxsrm0dweZ0yr7EhZv+eo/VYRr9HyszvJUiONo7LhRgLChOgOY9l nofAsu5PzTfPkoldWrqbNgyrZvLI0UftgMPWCAnbrDrHerUVm3M1FEkEWdHHom1OzTzQsfR54F d+LwndRr9S2+d3sKLGx1ger6dE6+HPu2yhiFHmyNyk+8JUtZ61Fm2JjjWfQAx6RXwzbZyOyLxV XdI= WDCIronportException: Internal Received: from unknown (HELO redsun52) ([10.149.66.28]) by uls-op-cesaip02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Feb 2020 11:33:26 -0800 Date: Fri, 14 Feb 2020 19:33:23 +0000 (GMT) From: "Maciej W. Rozycki" To: gdb-patches@sourceware.org cc: Jim Wilson , Andrew Burgess , Palmer Dabbelt , Tom Tromey , guoren@kernel.org, lifang_xia@c-sky.com, yunhai_shang@c-sky.com, jiangshuai_li@c-sky.com Subject: [PATCH v7 2/2] gdbserver: Add RISC-V/Linux support In-Reply-To: Message-ID: References: User-Agent: Alpine 2.21 (LFD 202 2017-01-01) MIME-Version: 1.0 Implement RISC-V/Linux support for both RV64 and RV32 systems, including XML target description handling based on features determined, GPR and FPR regset support including dynamic sizing of the latter, and software breakpoint handling. Define two NT_FPREGSET regsets of a different size matching the FPR sizes supported for generic `gdbserver' code to pick from according to what the OS supplies. Also handle a glibc bug where ELF_NFPREG is defined in terms of NFPREG, however NFPREG is nowhere defined. 2020-02-14 Maciej W. Rozycki Andrew Burgess gdbserver/ * linux-riscv-low.cc: New file. * Makefile.in (SFILES): Add linux-riscv-low.cc, arch/riscv.c, and nat/riscv-linux-tdesc.c. * configure.srv (srv_tgtobj) (srv_linux_regsets, srv_linux_usrregs, srv_linux_thread_db): Define. --- Changes from v6: - Regenerate for the gdbserver/ move to the top level. - Use the .cc suffix following the rename of other files. Changes from v4: - Add 128-bit FP regset. Changes from v3: - Actually include changes from v2. Changes from v2: - Advance through the buffer accessed in `riscv_fill_fpregset' and `riscv_store_fpregset' so as to avoid doing a variable multiplication in a loop; rename the `regset' variable to `regbuf'. - Use OPTIONAL_REGS rather than FP_REGS as the type for the floating-point regsets. - Add comments throughout. Changes from v1: - Make `gdbserver' selected for automatic build in a RISC-V/Linux/native GDB configuration (thanks, Jim, for pointing this out!). - Remove most of `riscv_arch_setup' and use `riscv_linux_read_description' from 2/3 instead. - Stop using `elf_fpregset_t*' in favour to just a raw `gdb_byte *' buffer and size the regset according to the FPR size in `riscv_fill_fpregset' and `riscv_store_fpregset'. - Define 2 NT_FPREGSET regsets of a different size for generic `gdbserver' code to pick from according to what the OS supplies. --- gdbserver/Makefile.in | 3 gdbserver/configure.srv | 7 + gdbserver/linux-riscv-low.c | 279 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 289 insertions(+) create mode 100644 gdbserver/linux-riscv-low.c gdb-riscv-gdbserver-linux.diff Index: binutils-gdb/gdbserver/Makefile.in =================================================================== --- binutils-gdb.orig/gdbserver/Makefile.in +++ binutils-gdb/gdbserver/Makefile.in @@ -181,6 +181,7 @@ SFILES = \ $(srcdir)/linux-mips-low.cc \ $(srcdir)/linux-nios2-low.cc \ $(srcdir)/linux-ppc-low.cc \ + $(srcdir)/linux-riscv-low.cc \ $(srcdir)/linux-s390-low.cc \ $(srcdir)/linux-sh-low.cc \ $(srcdir)/linux-sparc-low.cc \ @@ -207,6 +208,7 @@ SFILES = \ $(srcdir)/../gdb/arch/arm-get-next-pcs.c \ $(srcdir)/../gdb/arch/arm-linux.c \ $(srcdir)/../gdb/arch/ppc-linux-common.c \ + $(srcdir)/../gdb/arch/riscv.c \ $(srcdir)/../gdbsupport/btrace-common.cc \ $(srcdir)/../gdbsupport/buffer.cc \ $(srcdir)/../gdbsupport/cleanups.cc \ @@ -240,6 +242,7 @@ SFILES = \ $(srcdir)/../gdb/nat/linux-personality.c \ $(srcdir)/../gdb/nat/mips-linux-watch.c \ $(srcdir)/../gdb/nat/ppc-linux.c \ + $(srcdir)/../gdb/nat/riscv-linux-tdesc.c \ $(srcdir)/../gdb/nat/fork-inferior.c \ $(srcdir)/../gdb/target/waitstatus.c Index: binutils-gdb/gdbserver/configure.srv =================================================================== --- binutils-gdb.orig/gdbserver/configure.srv +++ binutils-gdb/gdbserver/configure.srv @@ -271,6 +271,13 @@ case "${host}" in srv_xmlfiles="${srv_xmlfiles} rs6000/power-fpu.xml" srv_lynxos=yes ;; + riscv*-*-linux*) srv_tgtobj="arch/riscv.o nat/riscv-linux-tdesc.o" + srv_tgtobj="${srv_tgtobj} linux-riscv-low.o" + srv_tgtobj="${srv_tgtobj} ${srv_linux_obj}" + srv_linux_regsets=yes + srv_linux_usrregs=yes + srv_linux_thread_db=yes + ;; s390*-*-linux*) srv_regobj="s390-linux32.o" srv_regobj="${srv_regobj} s390-linux32v1.o" srv_regobj="${srv_regobj} s390-linux32v2.o" Index: binutils-gdb/gdbserver/linux-riscv-low.cc =================================================================== --- /dev/null +++ binutils-gdb/gdbserver/linux-riscv-low.cc @@ -0,0 +1,279 @@ +/* GNU/Linux/RISC-V specific low level interface, for the remote server + for GDB. + Copyright (C) 2020 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "server.h" + +#include "linux-low.h" +#include "tdesc.h" +#include "elf/common.h" +#include "nat/riscv-linux-tdesc.h" +#include "opcode/riscv.h" + +/* Work around glibc header breakage causing ELF_NFPREG not to be usable. */ +#ifndef NFPREG +# define NFPREG 33 +#endif + +/* Implementation of linux_target_ops method "arch_setup". */ + +static void +riscv_arch_setup () +{ + static const char *expedite_regs[] = { "sp", "pc", NULL }; + + const riscv_gdbarch_features features + = riscv_linux_read_features (lwpid_of (current_thread)); + target_desc *tdesc = riscv_create_target_description (features); + + if (!tdesc->expedite_regs) + init_target_desc (tdesc, expedite_regs); + current_process ()->tdesc = tdesc; +} + +/* Collect GPRs from REGCACHE into BUF. */ + +static void +riscv_fill_gregset (struct regcache *regcache, void *buf) +{ + const struct target_desc *tdesc = regcache->tdesc; + elf_gregset_t *regset = (elf_gregset_t *) buf; + int regno = find_regno (tdesc, "zero"); + int i; + + collect_register_by_name (regcache, "pc", *regset); + for (i = 1; i < ARRAY_SIZE (*regset); i++) + collect_register (regcache, regno + i, *regset + i); +} + +/* Supply GPRs from BUF into REGCACHE. */ + +static void +riscv_store_gregset (struct regcache *regcache, const void *buf) +{ + const elf_gregset_t *regset = (const elf_gregset_t *) buf; + const struct target_desc *tdesc = regcache->tdesc; + int regno = find_regno (tdesc, "zero"); + int i; + + supply_register_by_name (regcache, "pc", *regset); + supply_register_zeroed (regcache, regno); + for (i = 1; i < ARRAY_SIZE (*regset); i++) + supply_register (regcache, regno + i, *regset + i); +} + +/* Collect FPRs from REGCACHE into BUF. */ + +static void +riscv_fill_fpregset (struct regcache *regcache, void *buf) +{ + const struct target_desc *tdesc = regcache->tdesc; + int regno = find_regno (tdesc, "ft0"); + int flen = register_size (regcache->tdesc, regno); + gdb_byte *regbuf = (gdb_byte *) buf; + int i; + + for (i = 0; i < ELF_NFPREG - 1; i++, regbuf += flen) + collect_register (regcache, regno + i, regbuf); + collect_register_by_name (regcache, "fcsr", regbuf); +} + +/* Supply FPRs from BUF into REGCACHE. */ + +static void +riscv_store_fpregset (struct regcache *regcache, const void *buf) +{ + const struct target_desc *tdesc = regcache->tdesc; + int regno = find_regno (tdesc, "ft0"); + int flen = register_size (regcache->tdesc, regno); + const gdb_byte *regbuf = (const gdb_byte *) buf; + int i; + + for (i = 0; i < ELF_NFPREG - 1; i++, regbuf += flen) + supply_register (regcache, regno + i, regbuf); + supply_register_by_name (regcache, "fcsr", regbuf); +} + +/* RISC-V/Linux regsets. FPRs are optional and come in different sizes, + so define multiple regsets for them marking them all as OPTIONAL_REGS + rather than FP_REGS, so that "regsets_fetch_inferior_registers" picks + the right one according to size. */ +static struct regset_info riscv_regsets[] = { + { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS, + sizeof (elf_gregset_t), GENERAL_REGS, + riscv_fill_gregset, riscv_store_gregset }, + { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_FPREGSET, + sizeof (struct __riscv_mc_q_ext_state), OPTIONAL_REGS, + riscv_fill_fpregset, riscv_store_fpregset }, + { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_FPREGSET, + sizeof (struct __riscv_mc_d_ext_state), OPTIONAL_REGS, + riscv_fill_fpregset, riscv_store_fpregset }, + { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_FPREGSET, + sizeof (struct __riscv_mc_f_ext_state), OPTIONAL_REGS, + riscv_fill_fpregset, riscv_store_fpregset }, + NULL_REGSET +}; + +/* RISC-V/Linux regset information. */ +static struct regsets_info riscv_regsets_info = + { + riscv_regsets, /* regsets */ + 0, /* num_regsets */ + NULL, /* disabled_regsets */ + }; + +/* Definition of linux_target_ops data member "regs_info". */ +static struct regs_info riscv_regs = + { + NULL, /* regset_bitmap */ + NULL, /* usrregs */ + &riscv_regsets_info, + }; + +/* Implementation of linux_target_ops method "regs_info". */ + +static const struct regs_info * +riscv_regs_info () +{ + return &riscv_regs; +} + +/* Implementation of linux_target_ops method "fetch_register". */ + +static int +riscv_fetch_register (struct regcache *regcache, int regno) +{ + const struct target_desc *tdesc = regcache->tdesc; + + if (regno != find_regno (tdesc, "zero")) + return 0; + supply_register_zeroed (regcache, regno); + return 1; +} + +/* Implementation of linux_target_ops method "get_pc". */ + +static CORE_ADDR +riscv_get_pc (struct regcache *regcache) +{ + elf_gregset_t regset; + + if (sizeof (regset[0]) == 8) + return linux_get_pc_64bit (regcache); + else + return linux_get_pc_32bit (regcache); +} + +/* Implementation of linux_target_ops method "set_pc". */ + +static void +riscv_set_pc (struct regcache *regcache, CORE_ADDR newpc) +{ + elf_gregset_t regset; + + if (sizeof (regset[0]) == 8) + linux_set_pc_64bit (regcache, newpc); + else + linux_set_pc_32bit (regcache, newpc); +} + +/* Correct in either endianness. */ +static const uint16_t riscv_ibreakpoint[] = { 0x0073, 0x0010 }; +static const uint16_t riscv_cbreakpoint = 0x9002; + +/* Implementation of linux_target_ops method "breakpoint_kind_from_pc". */ + +static int +riscv_breakpoint_kind_from_pc (CORE_ADDR *pcptr) +{ + union + { + gdb_byte bytes[2]; + uint16_t insn; + } + buf; + + if (target_read_memory (*pcptr, buf.bytes, sizeof (buf.insn)) == 0 + && riscv_insn_length (buf.insn == sizeof (riscv_ibreakpoint))) + return sizeof (riscv_ibreakpoint); + else + return sizeof (riscv_cbreakpoint); +} + +/* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */ + +static const gdb_byte * +riscv_sw_breakpoint_from_kind (int kind, int *size) +{ + *size = kind; + switch (kind) + { + case sizeof (riscv_ibreakpoint): + return (const gdb_byte *) &riscv_ibreakpoint; + default: + return (const gdb_byte *) &riscv_cbreakpoint; + } +} + +/* Implementation of linux_target_ops method "breakpoint_at". */ + +static int +riscv_breakpoint_at (CORE_ADDR pc) +{ + union + { + gdb_byte bytes[2]; + uint16_t insn; + } + buf; + + if (target_read_memory (pc, buf.bytes, sizeof (buf.insn)) == 0 + && (buf.insn == riscv_cbreakpoint + || (buf.insn == riscv_ibreakpoint[0] + && target_read_memory (pc + sizeof (buf.insn), buf.bytes, + sizeof (buf.insn)) == 0 + && buf.insn == riscv_ibreakpoint[1]))) + return 1; + else + return 0; +} + +/* RISC-V/Linux target operations. */ +struct linux_target_ops the_low_target = +{ + riscv_arch_setup, + riscv_regs_info, + NULL, /* cannot_fetch_register */ + NULL, /* cannot_store_register */ + riscv_fetch_register, + riscv_get_pc, + riscv_set_pc, + riscv_breakpoint_kind_from_pc, + riscv_sw_breakpoint_from_kind, + NULL, /* get_next_pcs */ + 0, /* decr_pc_after_break */ + riscv_breakpoint_at, +}; + +/* Initialize the RISC-V/Linux target. */ + +void +initialize_low_arch () +{ + initialize_regsets_info (&riscv_regsets_info); +}