From patchwork Mon Jun 13 12:38:33 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nick Clifton X-Patchwork-Id: 13041 Received: (qmail 56499 invoked by alias); 13 Jun 2016 12:38:49 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 56396 invoked by uid 89); 13 Jun 2016 12:38:48 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.3 required=5.0 tests=BAYES_00, RP_MATCHES_RCVD, SPF_HELO_PASS autolearn=ham version=3.3.2 spammy=Hx-languages-length:2330, held X-HELO: mx1.redhat.com Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Mon, 13 Jun 2016 12:38:38 +0000 Received: from int-mx14.intmail.prod.int.phx2.redhat.com (int-mx14.intmail.prod.int.phx2.redhat.com [10.5.11.27]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 590133B716; Mon, 13 Jun 2016 12:38:37 +0000 (UTC) Received: from localhost.localdomain (vpn1-6-128.ams2.redhat.com [10.36.6.128]) by int-mx14.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u5DCcYkm028469 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 13 Jun 2016 08:38:36 -0400 Subject: Re: [PATCH] aarch64 sim big-endian support To: Jim Wilson , gdb-patches@sourceware.org References: From: Nick Clifton Message-ID: Date: Mon, 13 Jun 2016 13:38:33 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.1.0 MIME-Version: 1.0 In-Reply-To: Hi Jim, > ping oops - sorry. > for the attachment, see > https://sourceware.org/ml/gdb-patches/2016-06/msg00046.html Did you see Mike Frysinger's comment about not changing global variables ? I think that I agree with this comment, although I could not find the raw opcode reading functions to which he was referring, (unless he meant sim_core_read_buffer), so would you mind trying out this variation of your patch to see if it works instead ? Cheers Nick diff --git a/sim/aarch64/memory.c b/sim/aarch64/memory.c index 50f4837..f7eea22 100644 --- a/sim/aarch64/memory.c +++ b/sim/aarch64/memory.c @@ -78,6 +78,20 @@ FETCH_FUNC32 (int32_t, int16_t, s16, 2) FETCH_FUNC32 (uint32_t, uint8_t, u8, 1) FETCH_FUNC32 (int32_t, int8_t, s8, 1) +/* Specialized version of aarch64_get_mem_u32 for fetching instructions + which are always held in little endian order even on big-endian + configured targets. */ + +uint32_t +aarch64_get_instruction (sim_cpu *cpu, uint64_t address) +{ + uint32_t val = aarch64_get_mem_u32 (cpu, address); + + if (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) + val = _SWAP_4 (val); + return val; +} + void aarch64_get_mem_long_double (sim_cpu *cpu, uint64_t address, FRegister *a) { diff --git a/sim/aarch64/memory.h b/sim/aarch64/memory.h index 3f63973..3559245 100644 --- a/sim/aarch64/memory.h +++ b/sim/aarch64/memory.h @@ -37,6 +37,7 @@ extern uint32_t aarch64_get_mem_u8 (sim_cpu *, uint64_t); extern int32_t aarch64_get_mem_s8 (sim_cpu *, uint64_t); extern void aarch64_get_mem_blk (sim_cpu *, uint64_t, char *, unsigned); extern const char * aarch64_get_mem_ptr (sim_cpu *, uint64_t); +extern uint32_t aarch64_get_instruction (sim_cpu *, uint64_t); extern void aarch64_set_mem_long_double (sim_cpu *, uint64_t, FRegister); extern void aarch64_set_mem_u64 (sim_cpu *, uint64_t, uint64_t); diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c index 88cb03d..c70fd96 100644 --- a/sim/aarch64/simulator.c +++ b/sim/aarch64/simulator.c @@ -14083,7 +14083,7 @@ aarch64_step (sim_cpu *cpu) return FALSE; aarch64_set_next_PC (cpu, pc + 4); - aarch64_get_instr (cpu) = aarch64_get_mem_u32 (cpu, pc); + aarch64_get_instr (cpu) = aarch64_get_instruction (cpu, pc); TRACE_INSN (cpu, " pc = %" PRIx64 " instr = %08x", pc, aarch64_get_instr (cpu));