From patchwork Mon Dec 5 12:28:45 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Hayward X-Patchwork-Id: 18193 Received: (qmail 17052 invoked by alias); 5 Dec 2016 12:29:05 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 17029 invoked by uid 89); 5 Dec 2016 12:29:04 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-4.5 required=5.0 tests=BAYES_00, KAM_LOTSOFHASH, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 spammy=doctype, !doctype, 81, 6, patsubst X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 05 Dec 2016 12:28:54 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 058D215AB; Mon, 5 Dec 2016 04:28:53 -0800 (PST) Received: from [10.45.32.207] (e105284-mac.manchester.arm.com [10.45.32.207]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 482ED3F445 for ; Mon, 5 Dec 2016 04:28:50 -0800 (PST) User-Agent: Microsoft-MacOutlook/14.7.0.161029 Date: Mon, 05 Dec 2016 12:28:45 +0000 Subject: [PATCH 5/8] AARCH64 SVE: Add SVE feature From: Alan Hayward To: Message-ID: Mime-version: 1.0 Content-type: text/plain; charset="UTF-8" Content-transfer-encoding: 7bit This is part of a series adding AARCH64 SVE support to gdb and gdbserver. This patch adds the SVE feature. This code sets size of the variable registers to 64bits for the Z registers and 8bits for the P registers. It will be the job of the aarch64 target code (in a later patch in the series) to scale the Z and P registers to the correct size using the integer scalar VG. VG is added as a register as this is used the the DWARF VG register and is also very useful for gdb end users. This feature will remain unused until a later patch in the series. Tested on x86 and aarch64. Ok to commit? Alan. diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo index 6ad275400929647b0e97cbb4920e21bec8e34366..e951234d3a85f7548cce3626bcba13f27 33f8850 100644 --- a/gdb/doc/gdb.texinfo +++ b/gdb/doc/gdb.texinfo @@ -40982,6 +40982,10 @@ The @samp{org.gnu.gdb.aarch64.fpu} feature is optional. If present, it should contain registers @samp{v0} through @samp{v31}, @samp{fpsr}, and @samp{fpcr}. +The @samp{org.gnu.gdb.aarch64.sve} feature is optional. If present, +it should contain registers @samp{z0} through @samp{z31}, @samp{p0} +through @samp{p15}, @samp{ffr} and @samp{vg}. + @node ARC Features @subsection ARC Features @cindex target descriptions, ARC Features diff --git a/gdb/features/Makefile b/gdb/features/Makefile index 30eed5db6715fada86ec075af526c54f18e3cd91..9546175836cb1e775379f306f072635b1 80a65c6 100644 --- a/gdb/features/Makefile +++ b/gdb/features/Makefile @@ -43,7 +43,7 @@ # # make GDB=/path/to/gdb XMLTOC="xml files" cfiles -WHICH = aarch64 \ +WHICH = aarch64 aarch64-sve \ arm/arm-with-iwmmxt arm/arm-with-vfpv2 arm/arm-with-vfpv3 \ arm/arm-with-neon \ i386/i386 i386/i386-linux \ @@ -81,6 +81,7 @@ WHICH = aarch64 \ # Record which registers should be sent to GDB by default after stop. aarch64-expedite = x29,sp,pc +aarch64-sve-expedite = x29,sp,pc,vg arm-expedite = r11,sp,pc i386-expedite = ebp,esp,eip amd64-expedite = rbp,rsp,rip @@ -127,6 +128,7 @@ OUTPUTS = $(patsubst %,$(outdir)/%.dat,$(WHICH)) # to make on the command line. XMLTOC = \ aarch64.xml \ + aarch64-sve.xml \ arc-v2.xml \ arc-arcompact.xml \ arm/arm-with-iwmmxt.xml \ diff --git a/gdb/features/aarch64-sve-core.xml b/gdb/features/aarch64-sve-core.xml new file mode 100644 index 0000000000000000000000000000000000000000..d990aebfa1d8d17cc53a70a6c7517533f 8e369b9 --- /dev/null +++ b/gdb/features/aarch64-sve-core.xml @@ -0,0 +1,105 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb/features/aarch64-sve.c b/gdb/features/aarch64-sve.c new file mode 100644 index 0000000000000000000000000000000000000000..13dd58e64c2cb54ee14edc002d1aa4316 7f383fa --- /dev/null +++ b/gdb/features/aarch64-sve.c @@ -0,0 +1,198 @@ +/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro: + Original: aarch64-sve.xml */ + +#include "defs.h" +#include "osabi.h" +#include "target-descriptions.h" + +struct target_desc *tdesc_aarch64_sve; +static void +initialize_tdesc_aarch64_sve (void) +{ + struct target_desc *result = allocate_target_description (); + struct tdesc_feature *feature; + struct tdesc_type *field_type; + struct tdesc_type *type; + + set_tdesc_architecture (result, bfd_scan_arch ("aarch64")); + + feature = tdesc_create_feature (result, "org.gnu.gdb.aarch64.core"); + type = tdesc_create_flags (feature, "cpsr_flags", 4); + tdesc_add_flag (type, 0, "SP"); + tdesc_add_bitfield (type, "", 1, 1); + tdesc_add_bitfield (type, "EL", 2, 3); + tdesc_add_flag (type, 4, "nRW"); + tdesc_add_bitfield (type, "", 5, 5); + tdesc_add_flag (type, 6, "F"); + tdesc_add_flag (type, 7, "I"); + tdesc_add_flag (type, 8, "A"); + tdesc_add_flag (type, 9, "D"); + tdesc_add_flag (type, 20, "IL"); + tdesc_add_flag (type, 21, "SS"); + tdesc_add_flag (type, 28, "V"); + tdesc_add_flag (type, 29, "C"); + tdesc_add_flag (type, 30, "Z"); + tdesc_add_flag (type, 31, "N"); + + tdesc_create_reg (feature, "x0", 0, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "x1", 1, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "x2", 2, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "x3", 3, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "x4", 4, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "x5", 5, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "x6", 6, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "x7", 7, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "x8", 8, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "x9", 9, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "x10", 10, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "x11", 11, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "x12", 12, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "x13", 13, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "x14", 14, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "x15", 15, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "x16", 16, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "x17", 17, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "x18", 18, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "x19", 19, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "x20", 20, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "x21", 21, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "x22", 22, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "x23", 23, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "x24", 24, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "x25", 25, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "x26", 26, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "x27", 27, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "x28", 28, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "x29", 29, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "x30", 30, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "sp", 31, 1, NULL, 64, "data_ptr"); + tdesc_create_reg (feature, "pc", 32, 1, NULL, 64, "code_ptr"); + tdesc_create_reg (feature, "cpsr", 33, 1, NULL, 32, "cpsr_flags"); + + feature = tdesc_create_feature (result, "org.gnu.gdb.aarch64.sve"); + field_type = tdesc_named_type (feature, "ieee_double"); + tdesc_create_vector (feature, "svevdf", field_type, 1); + + field_type = tdesc_named_type (feature, "uint64"); + tdesc_create_vector (feature, "svevdu", field_type, 1); + + field_type = tdesc_named_type (feature, "int64"); + tdesc_create_vector (feature, "svevds", field_type, 1); + + field_type = tdesc_named_type (feature, "ieee_single"); + tdesc_create_vector (feature, "svevsf", field_type, 2); + + field_type = tdesc_named_type (feature, "uint32"); + tdesc_create_vector (feature, "svevsu", field_type, 2); + + field_type = tdesc_named_type (feature, "int32"); + tdesc_create_vector (feature, "svevss", field_type, 2); + + field_type = tdesc_named_type (feature, "uint16"); + tdesc_create_vector (feature, "svevhu", field_type, 4); + + field_type = tdesc_named_type (feature, "int16"); + tdesc_create_vector (feature, "svevhs", field_type, 4); + + field_type = tdesc_named_type (feature, "uint8"); + tdesc_create_vector (feature, "svevbu", field_type, 8); + + field_type = tdesc_named_type (feature, "int8"); + tdesc_create_vector (feature, "svevbs", field_type, 8); + + type = tdesc_create_union (feature, "svevnd"); + field_type = tdesc_named_type (feature, "svevdf"); + tdesc_add_field (type, "f", field_type); + field_type = tdesc_named_type (feature, "svevdu"); + tdesc_add_field (type, "u", field_type); + field_type = tdesc_named_type (feature, "svevds"); + tdesc_add_field (type, "s", field_type); + + type = tdesc_create_union (feature, "svevns"); + field_type = tdesc_named_type (feature, "svevsf"); + tdesc_add_field (type, "f", field_type); + field_type = tdesc_named_type (feature, "svevsu"); + tdesc_add_field (type, "u", field_type); + field_type = tdesc_named_type (feature, "svevss"); + tdesc_add_field (type, "s", field_type); + + type = tdesc_create_union (feature, "svevnh"); + field_type = tdesc_named_type (feature, "svevhu"); + tdesc_add_field (type, "u", field_type); + field_type = tdesc_named_type (feature, "svevhs"); + tdesc_add_field (type, "s", field_type); + + type = tdesc_create_union (feature, "svevnb"); + field_type = tdesc_named_type (feature, "svevbu"); + tdesc_add_field (type, "u", field_type); + field_type = tdesc_named_type (feature, "svevbs"); + tdesc_add_field (type, "s", field_type); + + type = tdesc_create_union (feature, "svev"); + field_type = tdesc_named_type (feature, "svevnd"); + tdesc_add_field (type, "d", field_type); + field_type = tdesc_named_type (feature, "svevns"); + tdesc_add_field (type, "s", field_type); + field_type = tdesc_named_type (feature, "svevnh"); + tdesc_add_field (type, "h", field_type); + field_type = tdesc_named_type (feature, "svevnb"); + tdesc_add_field (type, "b", field_type); + + field_type = tdesc_named_type (feature, "uint8"); + tdesc_create_vector (feature, "svep", field_type, 1); + + tdesc_create_reg (feature, "z0", 34, 1, NULL, 64, "svev"); + tdesc_create_reg (feature, "z1", 35, 1, NULL, 64, "svev"); + tdesc_create_reg (feature, "z2", 36, 1, NULL, 64, "svev"); + tdesc_create_reg (feature, "z3", 37, 1, NULL, 64, "svev"); + tdesc_create_reg (feature, "z4", 38, 1, NULL, 64, "svev"); + tdesc_create_reg (feature, "z5", 39, 1, NULL, 64, "svev"); + tdesc_create_reg (feature, "z6", 40, 1, NULL, 64, "svev"); + tdesc_create_reg (feature, "z7", 41, 1, NULL, 64, "svev"); + tdesc_create_reg (feature, "z8", 42, 1, NULL, 64, "svev"); + tdesc_create_reg (feature, "z9", 43, 1, NULL, 64, "svev"); + tdesc_create_reg (feature, "z10", 44, 1, NULL, 64, "svev"); + tdesc_create_reg (feature, "z11", 45, 1, NULL, 64, "svev"); + tdesc_create_reg (feature, "z12", 46, 1, NULL, 64, "svev"); + tdesc_create_reg (feature, "z13", 47, 1, NULL, 64, "svev"); + tdesc_create_reg (feature, "z14", 48, 1, NULL, 64, "svev"); + tdesc_create_reg (feature, "z15", 49, 1, NULL, 64, "svev"); + tdesc_create_reg (feature, "z16", 50, 1, NULL, 64, "svev"); + tdesc_create_reg (feature, "z17", 51, 1, NULL, 64, "svev"); + tdesc_create_reg (feature, "z18", 52, 1, NULL, 64, "svev"); + tdesc_create_reg (feature, "z19", 53, 1, NULL, 64, "svev"); + tdesc_create_reg (feature, "z20", 54, 1, NULL, 64, "svev"); + tdesc_create_reg (feature, "z21", 55, 1, NULL, 64, "svev"); + tdesc_create_reg (feature, "z22", 56, 1, NULL, 64, "svev"); + tdesc_create_reg (feature, "z23", 57, 1, NULL, 64, "svev"); + tdesc_create_reg (feature, "z24", 58, 1, NULL, 64, "svev"); + tdesc_create_reg (feature, "z25", 59, 1, NULL, 64, "svev"); + tdesc_create_reg (feature, "z26", 60, 1, NULL, 64, "svev"); + tdesc_create_reg (feature, "z27", 61, 1, NULL, 64, "svev"); + tdesc_create_reg (feature, "z28", 62, 1, NULL, 64, "svev"); + tdesc_create_reg (feature, "z29", 63, 1, NULL, 64, "svev"); + tdesc_create_reg (feature, "z30", 64, 1, NULL, 64, "svev"); + tdesc_create_reg (feature, "z31", 65, 1, NULL, 64, "svev"); + tdesc_create_reg (feature, "fpsr", 66, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "fpcr", 67, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "p0", 68, 1, NULL, 8, "svep"); + tdesc_create_reg (feature, "p1", 69, 1, NULL, 8, "svep"); + tdesc_create_reg (feature, "p2", 70, 1, NULL, 8, "svep"); + tdesc_create_reg (feature, "p3", 71, 1, NULL, 8, "svep"); + tdesc_create_reg (feature, "p4", 72, 1, NULL, 8, "svep"); + tdesc_create_reg (feature, "p5", 73, 1, NULL, 8, "svep"); + tdesc_create_reg (feature, "p6", 74, 1, NULL, 8, "svep"); + tdesc_create_reg (feature, "p7", 75, 1, NULL, 8, "svep"); + tdesc_create_reg (feature, "p8", 76, 1, NULL, 8, "svep"); + tdesc_create_reg (feature, "p9", 77, 1, NULL, 8, "svep"); + tdesc_create_reg (feature, "p10", 78, 1, NULL, 8, "svep"); + tdesc_create_reg (feature, "p11", 79, 1, NULL, 8, "svep"); + tdesc_create_reg (feature, "p12", 80, 1, NULL, 8, "svep"); + tdesc_create_reg (feature, "p13", 81, 1, NULL, 8, "svep"); + tdesc_create_reg (feature, "p14", 82, 1, NULL, 8, "svep"); + tdesc_create_reg (feature, "p15", 83, 1, NULL, 8, "svep"); + tdesc_create_reg (feature, "ffr", 84, 1, NULL, 8, "svep"); + tdesc_create_reg (feature, "vg", 85, 1, NULL, 64, "int"); + + tdesc_aarch64_sve = result; +} diff --git a/gdb/features/aarch64-sve.xml b/gdb/features/aarch64-sve.xml new file mode 100644 index 0000000000000000000000000000000000000000..47dcb94ba62651132531cd09ce86ae21c 8131fb1 --- /dev/null +++ b/gdb/features/aarch64-sve.xml @@ -0,0 +1,14 @@ + + + + + + aarch64 + + + diff --git a/gdb/gdbserver/Makefile.in b/gdb/gdbserver/Makefile.in index 5316c95b67f04591c448a8a14b4ed3cac0092666..3b175caeb0807fd315baa35dbb8e34065 32a335e 100644 --- a/gdb/gdbserver/Makefile.in +++ b/gdb/gdbserver/Makefile.in @@ -418,7 +418,7 @@ clean: rm -f version.c rm -f gdbserver$(EXEEXT) gdbreplay$(EXEEXT) core make.log rm -f $(IPA_LIB) - rm -f aarch64.c + rm -f aarch64.c aarch64-sve.c rm -f reg-arm.c reg-bfin.c i386.c reg-ia64.c reg-m32r.c reg-m68k.c rm -f reg-sh.c reg-sparc.c reg-spu.c amd64.c i386-linux.c rm -f reg-cris.c reg-crisv32.c amd64-linux.c reg-xtensa.c @@ -607,6 +607,9 @@ linux-aarch64-ipa.o: linux-aarch64-ipa.c aarch64-ipa.o: aarch64.c $(IPAGENT_COMPILE) $< $(POSTCOMPILE) +aarch64-sve-ipa.o: aarch64-sve.c + $(IPAGENT_COMPILE) $< + $(POSTCOMPILE) linux-s390-ipa.o: linux-s390-ipa.c $(IPAGENT_COMPILE) $< $(POSTCOMPILE) @@ -870,6 +873,8 @@ aarch64-insn.o: ../arch/aarch64-insn.c aarch64.c : $(srcdir)/../regformats/aarch64.dat $(regdat_sh) $(SHELL) $(regdat_sh) $(srcdir)/../regformats/aarch64.dat aarch64.c +aarch64-sve.c : $(srcdir)/../regformats/aarch64-sve.dat $(regdat_sh) + $(SHELL) $(regdat_sh) $(srcdir)/../regformats/aarch64-sve.dat aarch64-sve.c reg-arm.c : $(srcdir)/../regformats/reg-arm.dat $(regdat_sh) $(SHELL) $(regdat_sh) $(srcdir)/../regformats/reg-arm.dat reg-arm.c arm-with-iwmmxt.c : $(srcdir)/../regformats/arm/arm-with-iwmmxt.dat $(regdat_sh) diff --git a/gdb/gdbserver/configure.srv b/gdb/gdbserver/configure.srv index 32675995fa6c2dcb1af059e33f88c5dd053d63a3..a8d782be24a03333c273fa49ef2275049 96d73f6 100644 --- a/gdb/gdbserver/configure.srv +++ b/gdb/gdbserver/configure.srv @@ -52,6 +52,7 @@ case "${target}" in aarch64*-*-linux*) srv_regobj="aarch64.o" srv_regobj="${srv_regobj} arm-with-neon.o" + srv_regobj="${srv_regobj} aarch64-sve.o" srv_tgtobj="linux-aarch64-low.o aarch64-linux-hw-point.o" srv_tgtobj="$srv_tgtobj linux-aarch32-low.o" srv_tgtobj="${srv_tgtobj} arm.o" @@ -61,11 +62,12 @@ case "${target}" in srv_xmlfiles="aarch64.xml" srv_xmlfiles="${srv_xmlfiles} aarch64-core.xml" srv_xmlfiles="${srv_xmlfiles} aarch64-fpu.xml" - srv_xmlfiles="${srv_xmlfiles} arm/arm-core.xml arm/arm-vfpv3.xml" + srv_xmlfiles="${srv_xmlfiles} aarch64-sve.xml" + srv_xmlfiles="${srv_xmlfiles} aarch64-sve-core.xml" srv_xmlfiles="${srv_xmlfiles} arm/arm-core.xml arm/arm-vfpv3.xml" srv_xmlfiles="${srv_xmlfiles} arm/arm-with-neon.xml" srv_linux_regsets=yes srv_linux_thread_db=yes - ipa_obj="linux-aarch64-ipa.o aarch64-ipa.o" + ipa_obj="linux-aarch64-ipa.o aarch64-ipa.o aarch64-sve-ipa.o" ;; arm*-*-linux*) srv_regobj="reg-arm.o arm-with-iwmmxt.o" srv_regobj="${srv_regobj} arm-with-vfpv2.o" diff --git a/gdb/regformats/aarch64-sve.dat b/gdb/regformats/aarch64-sve.dat new file mode 100644 index 0000000000000000000000000000000000000000..91f994b966ee6102542af94c3c758dcd7 d3b795b --- /dev/null +++ b/gdb/regformats/aarch64-sve.dat @@ -0,0 +1,91 @@ +# THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi :set ro: +# Generated from: aarch64-sve.xml +name:aarch64_sve +xmltarget:aarch64-sve.xml +expedite:x29,sp,pc,vg +64:x0 +64:x1 +64:x2 +64:x3 +64:x4 +64:x5 +64:x6 +64:x7 +64:x8 +64:x9 +64:x10 +64:x11 +64:x12 +64:x13 +64:x14 +64:x15 +64:x16 +64:x17 +64:x18 +64:x19 +64:x20 +64:x21 +64:x22 +64:x23 +64:x24 +64:x25 +64:x26 +64:x27 +64:x28 +64:x29 +64:x30 +64:sp +64:pc +32:cpsr +64:z0 +64:z1 +64:z2 +64:z3 +64:z4 +64:z5 +64:z6 +64:z7 +64:z8 +64:z9 +64:z10 +64:z11 +64:z12 +64:z13 +64:z14 +64:z15 +64:z16 +64:z17 +64:z18 +64:z19 +64:z20 +64:z21 +64:z22 +64:z23 +64:z24 +64:z25 +64:z26 +64:z27 +64:z28 +64:z29 +64:z30 +64:z31 +32:fpsr +32:fpcr +8:p0 +8:p1 +8:p2 +8:p3 +8:p4 +8:p5 +8:p6 +8:p7 +8:p8 +8:p9 +8:p10 +8:p11 +8:p12 +8:p13 +8:p14 +8:p15 +8:ffr +64:vg