| Message ID | CAPpQWtCBru_0S9ixocAzy7jWSy9SjXXWMhtY+2W1ePKiq7x69A@mail.gmail.com |
|---|---|
| State | New |
| Headers |
Return-Path: <gdb-patches-bounces+patchwork=sourceware.org@sourceware.org> X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C0BFD3959C5D for <patchwork@sourceware.org>; Tue, 6 Dec 2022 07:00:08 +0000 (GMT) X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from mail-ot1-x330.google.com (mail-ot1-x330.google.com [IPv6:2607:f8b0:4864:20::330]) by sourceware.org (Postfix) with ESMTPS id 0DAD43959C4B for <gdb-patches@sourceware.org>; Tue, 6 Dec 2022 06:59:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 0DAD43959C4B Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-ot1-x330.google.com with SMTP id s30-20020a056830439e00b0067052c70922so1928853otv.11 for <gdb-patches@sourceware.org>; Mon, 05 Dec 2022 22:59:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=pc2myuoQqBdR6hZQIGVDXKjql32qzKn9kIOnpcBReYc=; b=j17oX9dYa0ryGjn4Yw1oJ94Oizp2KybKCtHXcWtO29C6px+rH8gMKhEeH3CSOh5JKL t6dWktz70YQxo6lohh4DzYqd/9q36l6fDhOhPcPPi9HSUifFWqJPZDRRfwObVO+Jpj0G uszMzMObhWJawDA0GqJVTZ/6D4hdjWBcC7BWLqy1T8iREa2aIpnoD8TI71UqbyOZERvc OhjDDg3jjRep2u4gUkeK7xPOjr5EpY03J1UOQqTZEseb/nej9efHmkyxD3zQnLABoWCd 6lfKzVGmV2e0lznjkH3W12ne6h9xrzlIHwgONUoLZJ8oucdyjQFI0scOdmc9H5DLamuR uPGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=pc2myuoQqBdR6hZQIGVDXKjql32qzKn9kIOnpcBReYc=; b=IU5l2UAXUtDFSMxem7Cxlk0D8OV+lbZYqAozI0BJGJ5XHAHOnsLODEt0EDRuN02lFe jCr1hK5DFxfiSHloNG7r5PxkPtJGmaugyBgTG2UirlzuT323WpL0tVL42s+X7iESlRox STnfZBcE30N/NGJVYbJYeJYut41IipHA34tbasNyZ5y6/GB7oki+qB/6MpO9SMjy+xAA cub+kD5zkSnpCZyivmwGoobM3+z7IynOqVoTBJ5UC12wtPdNlAVQ4BZ2iOS+NgfagZme uMTmb4WzSpiOU7DrM8Z3YSCqJb/7Cd6i0wssZp94FQ9JxGYG1FUFtlKx4+sQZ0hRSnPJ AeEQ== X-Gm-Message-State: ANoB5pnAEcZXV4WKJgqsyCPfB7luVKzRC5L3xcUyhQiLZwhnUpS9lMh9 N5LV2bmVF2cm18fQBjgxYlVLpRLT1D0m8RC71ozwO+eaRberbw== X-Google-Smtp-Source: AA0mqf50P2l12kUJfTWUdBsYbG58j+L5yE034Sri21nAK9nwC58HvtpmRzkbowBGNPAJi7kqDFTMCYOx0Sp4BzJEZiU= X-Received: by 2002:a9d:61d6:0:b0:66d:685d:a138 with SMTP id h22-20020a9d61d6000000b0066d685da138mr43109468otk.208.1670309994234; Mon, 05 Dec 2022 22:59:54 -0800 (PST) MIME-Version: 1.0 References: <20221206053947.821648-1-zengxiao@eswincomputing.com> In-Reply-To: <20221206053947.821648-1-zengxiao@eswincomputing.com> From: Nelson Chu <nelson@rivosinc.com> Date: Tue, 6 Dec 2022 14:59:43 +0800 Message-ID: <CAPpQWtCBru_0S9ixocAzy7jWSy9SjXXWMhtY+2W1ePKiq7x69A@mail.gmail.com> Subject: Fwd: [PATCH] RISC-V: Correction of machine registers mapping to dwarf registers To: gdb-patches@sourceware.org Cc: Andrew Burgess <aburgess@redhat.com> Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-9.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list <gdb-patches.sourceware.org> List-Unsubscribe: <https://sourceware.org/mailman/options/gdb-patches>, <mailto:gdb-patches-request@sourceware.org?subject=unsubscribe> List-Archive: <https://sourceware.org/pipermail/gdb-patches/> List-Post: <mailto:gdb-patches@sourceware.org> List-Help: <mailto:gdb-patches-request@sourceware.org?subject=help> List-Subscribe: <https://sourceware.org/mailman/listinfo/gdb-patches>, <mailto:gdb-patches-request@sourceware.org?subject=subscribe> Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org Sender: "Gdb-patches" <gdb-patches-bounces+patchwork=sourceware.org@sourceware.org> |
| Series |
RISC-V: Correction of machine registers mapping to dwarf registers
|
|
Commit Message
Nelson Chu
Dec. 6, 2022, 6:59 a.m. UTC
Forward to gdb mailing list and cc Andrew since it seems under the gdb folder.
Thanks
Nelson
---------- Forwarded message ---------
From: Xiao Zeng <zengxiao@eswincomputing.com>
Date: Tue, Dec 6, 2022 at 1:39 PM
Subject: [PATCH] RISC-V: Correction of machine registers mapping to
dwarf registers
To: <binutils@sourceware.org>
Cc: <kito.cheng@gmail.com>, <palmer@dabbelt.com>,
<nelson@rivosinc.com>, Xiao Zeng <zengxiao@eswincomputing.com>
According to the riscv psabi, the mapping relationship between the
dwarf registers and the machine registers are as follows:
DWARF Number | Register Name | Description
0 - 31 | x0 - x31 | Integer Registers
32 - 63 | f0 - f31 | Floating-point Registers
* gdb/riscv-tdep.c (riscv_dwarf_reg_to_regnum): Correct mapping
boundary register.
---
gdb/riscv-tdep.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--
2.34.1
Comments
Nelson Chu <nelson@rivosinc.com> writes: > Forward to gdb mailing list and cc Andrew since it seems under the gdb folder. > > Thanks > Nelson > > ---------- Forwarded message --------- > From: Xiao Zeng <zengxiao@eswincomputing.com> > Date: Tue, Dec 6, 2022 at 1:39 PM > Subject: [PATCH] RISC-V: Correction of machine registers mapping to > dwarf registers > To: <binutils@sourceware.org> > Cc: <kito.cheng@gmail.com>, <palmer@dabbelt.com>, > <nelson@rivosinc.com>, Xiao Zeng <zengxiao@eswincomputing.com> > > > According to the riscv psabi, the mapping relationship between the > dwarf registers and the machine registers are as follows: > > DWARF Number | Register Name | Description > 0 - 31 | x0 - x31 | Integer Registers > 32 - 63 | f0 - f31 | Floating-point Registers > > * gdb/riscv-tdep.c (riscv_dwarf_reg_to_regnum): Correct mapping > boundary register. Thanks for catching this. I went ahead and merged this patch. Thanks, Andrew > --- > gdb/riscv-tdep.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c > index 0a050b272ff..a298623b449 100644 > --- a/gdb/riscv-tdep.c > +++ b/gdb/riscv-tdep.c > @@ -3623,10 +3623,10 @@ riscv_add_reggroups (struct gdbarch *gdbarch) > static int > riscv_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) > { > - if (reg < RISCV_DWARF_REGNUM_X31) > + if (reg <= RISCV_DWARF_REGNUM_X31) > return RISCV_ZERO_REGNUM + (reg - RISCV_DWARF_REGNUM_X0); > > - else if (reg < RISCV_DWARF_REGNUM_F31) > + else if (reg <= RISCV_DWARF_REGNUM_F31) > return RISCV_FIRST_FP_REGNUM + (reg - RISCV_DWARF_REGNUM_F0); > > else if (reg >= RISCV_DWARF_FIRST_CSR && reg <= RISCV_DWARF_LAST_CSR) > -- > 2.34.1
On Tue, Dec 6, 2022 at 12:00:00 AM Andrew Burgess <aburgess@redhat.com> wrote: > >Nelson Chu <nelson@rivosinc.com> writes: > >> Forward to gdb mailing list and cc Andrew since it seems under the gdb folder. >> I will mention the gdb patch in the correct mailing list next time，thanks Nelson. >> Thanks >> Nelson >> >> ---------- Forwarded message --------- >> From: Xiao Zeng <zengxiao@eswincomputing.com> >> Date: Tue, Dec 6, 2022 at 1:39 PM >> Subject: [PATCH] RISC-V: Correction of machine registers mapping to >> dwarf registers >> To: <binutils@sourceware.org> >> Cc: <kito.cheng@gmail.com>, <palmer@dabbelt.com>, >> <nelson@rivosinc.com>, Xiao Zeng <zengxiao@eswincomputing.com> >> >> >> According to the riscv psabi, the mapping relationship between the >> dwarf registers and the machine registers are as follows: >> >> DWARF Number | Register Name | Description >> 0 - 31 | x0 - x31 | Integer Registers >> 32 - 63 | f0 - f31 | Floating-point Registers >> >> * gdb/riscv-tdep.c (riscv_dwarf_reg_to_regnum): Correct mapping >> boundary register. > >Thanks for catching this. I went ahead and merged this patch. > >Thanks, >Andrew hi, Andrew I still don't know why gdb has a separate mailing list as a part of bintuils. Can you give me an explanation when you are free? Thanks Xiao > >> --- >> gdb/riscv-tdep.c | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c >> index 0a050b272ff..a298623b449 100644 >> --- a/gdb/riscv-tdep.c >> +++ b/gdb/riscv-tdep.c >> @@ -3623,10 +3623,10 @@ riscv_add_reggroups (struct gdbarch *gdbarch) >> static int >> riscv_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) >> { >> - if (reg < RISCV_DWARF_REGNUM_X31) >> + if (reg <= RISCV_DWARF_REGNUM_X31) >> return RISCV_ZERO_REGNUM + (reg - RISCV_DWARF_REGNUM_X0); >> >> - else if (reg < RISCV_DWARF_REGNUM_F31) >> + else if (reg <= RISCV_DWARF_REGNUM_F31) >> return RISCV_FIRST_FP_REGNUM + (reg - RISCV_DWARF_REGNUM_F0); >> >> else if (reg >= RISCV_DWARF_FIRST_CSR && reg <= RISCV_DWARF_LAST_CSR) >> -- >> 2.34.1
On Tue, Dec 6, 2022 at 5:46 PM Xiao Zeng <zengxiao@eswincomputing.com> wrote: > > On Tue, Dec 6, 2022 at 12:00:00 AM Andrew Burgess <aburgess@redhat.com> wrote: > > > >Nelson Chu <nelson@rivosinc.com> writes: > > > >> Forward to gdb mailing list and cc Andrew since it seems under the gdb folder. > >> > > I will mention the gdb patch in the correct mailing list next time，thanks Nelson. > > >> Thanks > >> Nelson > >> > >> ---------- Forwarded message --------- > >> From: Xiao Zeng <zengxiao@eswincomputing.com> > >> Date: Tue, Dec 6, 2022 at 1:39 PM > >> Subject: [PATCH] RISC-V: Correction of machine registers mapping to > >> dwarf registers > >> To: <binutils@sourceware.org> > >> Cc: <kito.cheng@gmail.com>, <palmer@dabbelt.com>, > >> <nelson@rivosinc.com>, Xiao Zeng <zengxiao@eswincomputing.com> > >> > >> > >> According to the riscv psabi, the mapping relationship between the > >> dwarf registers and the machine registers are as follows: > >> > >> DWARF Number | Register Name | Description > >> 0 - 31 | x0 - x31 | Integer Registers > >> 32 - 63 | f0 - f31 | Floating-point Registers > >> > >> * gdb/riscv-tdep.c (riscv_dwarf_reg_to_regnum): Correct mapping > >> boundary register. > > > >Thanks for catching this. I went ahead and merged this patch. > > > >Thanks, > >Andrew > > hi, Andrew > I still don't know why gdb has a separate mailing list as a part of bintuils. > Can you give me an explanation when you are free? Because technically they are separate projects with their own release schedules. Just happens they share the same repositories; mostly because BFD is common between the two. Thanks, Andrew > > Thanks > Xiao > > > > >> --- > >> gdb/riscv-tdep.c | 4 ++-- > >> 1 file changed, 2 insertions(+), 2 deletions(-) > >> > >> diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c > >> index 0a050b272ff..a298623b449 100644 > >> --- a/gdb/riscv-tdep.c > >> +++ b/gdb/riscv-tdep.c > >> @@ -3623,10 +3623,10 @@ riscv_add_reggroups (struct gdbarch *gdbarch) > >> static int > >> riscv_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) > >> { > >> - if (reg < RISCV_DWARF_REGNUM_X31) > >> + if (reg <= RISCV_DWARF_REGNUM_X31) > >> return RISCV_ZERO_REGNUM + (reg - RISCV_DWARF_REGNUM_X0); > >> > >> - else if (reg < RISCV_DWARF_REGNUM_F31) > >> + else if (reg <= RISCV_DWARF_REGNUM_F31) > >> return RISCV_FIRST_FP_REGNUM + (reg - RISCV_DWARF_REGNUM_F0); > >> > >> else if (reg >= RISCV_DWARF_FIRST_CSR && reg <= RISCV_DWARF_LAST_CSR) > >> -- > >> 2.34.1 > >
On Wed, Dec 7, 2022 at 09:50:00 AM Andrew Pinski <pinskia@gmail.com> wrote: > >On Tue, Dec 6, 2022 at 5:46 PM Xiao Zeng <zengxiao@eswincomputing.com> wrote: >> >> On Tue, Dec 6, 2022 at 12:00:00 AM Andrew Burgess <aburgess@redhat.com> wrote: >> > >> >Nelson Chu <nelson@rivosinc.com> writes: >> > >> >> Forward to gdb mailing list and cc Andrew since it seems under the gdb folder. >> >> >> >> I will mention the gdb patch in the correct mailing list next time，thanks Nelson. >> >> >> Thanks >> >> Nelson >> >> >> >> ---------- Forwarded message --------- >> >> From: Xiao Zeng <zengxiao@eswincomputing.com> >> >> Date: Tue, Dec 6, 2022 at 1:39 PM >> >> Subject: [PATCH] RISC-V: Correction of machine registers mapping to >> >> dwarf registers >> >> To: <binutils@sourceware.org> >> >> Cc: <kito.cheng@gmail.com>, <palmer@dabbelt.com>, >> >> <nelson@rivosinc.com>, Xiao Zeng <zengxiao@eswincomputing.com> >> >> >> >> >> >> According to the riscv psabi, the mapping relationship between the >> >> dwarf registers and the machine registers are as follows: >> >> >> >> DWARF Number | Register Name | Description >> >> 0 - 31 | x0 - x31 | Integer Registers >> >> 32 - 63 | f0 - f31 | Floating-point Registers >> >> >> >> * gdb/riscv-tdep.c (riscv_dwarf_reg_to_regnum): Correct mapping >> >> boundary register. >> > >> >Thanks for catching this. I went ahead and merged this patch. >> > >> >Thanks, >> >Andrew >> >> hi, Andrew >> I still don't know why gdb has a separate mailing list as a part of bintuils. >> Can you give me an explanation when you are free? > >Because technically they are separate projects with their own release >schedules. Just happens they share the same repositories; mostly >because BFD is common between the two. > >Thanks, >Andrew I see, thanks Andrew. Thanks Xiao > >> >> Thanks >> Xiao >> >> > >> >> --- >> >> gdb/riscv-tdep.c | 4 ++-- >> >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> >> >> diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c >> >> index 0a050b272ff..a298623b449 100644 >> >> --- a/gdb/riscv-tdep.c >> >> +++ b/gdb/riscv-tdep.c >> >> @@ -3623,10 +3623,10 @@ riscv_add_reggroups (struct gdbarch *gdbarch) >> >> static int >> >> riscv_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) >> >> { >> >> - if (reg < RISCV_DWARF_REGNUM_X31) >> >> + if (reg <= RISCV_DWARF_REGNUM_X31) >> >> return RISCV_ZERO_REGNUM + (reg - RISCV_DWARF_REGNUM_X0); >> >> >> >> - else if (reg < RISCV_DWARF_REGNUM_F31) >> >> + else if (reg <= RISCV_DWARF_REGNUM_F31) >> >> return RISCV_FIRST_FP_REGNUM + (reg - RISCV_DWARF_REGNUM_F0); >> >> >> >> else if (reg >= RISCV_DWARF_FIRST_CSR && reg <= RISCV_DWARF_LAST_CSR) >> >> -- >> >> 2.34.1 >> >>
diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index 0a050b272ff..a298623b449 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -3623,10 +3623,10 @@ riscv_add_reggroups (struct gdbarch *gdbarch) static int riscv_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) { - if (reg < RISCV_DWARF_REGNUM_X31) + if (reg <= RISCV_DWARF_REGNUM_X31) return RISCV_ZERO_REGNUM + (reg - RISCV_DWARF_REGNUM_X0); - else if (reg < RISCV_DWARF_REGNUM_F31) + else if (reg <= RISCV_DWARF_REGNUM_F31) return RISCV_FIRST_FP_REGNUM + (reg - RISCV_DWARF_REGNUM_F0); else if (reg >= RISCV_DWARF_FIRST_CSR && reg <= RISCV_DWARF_LAST_CSR)