From patchwork Sat Dec 24 22:24:15 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 18680 Received: (qmail 21476 invoked by alias); 24 Dec 2016 22:24:33 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 21461 invoked by uid 89); 24 Dec 2016 22:24:31 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=u64, m4s X-HELO: mail-yw0-f172.google.com Received: from mail-yw0-f172.google.com (HELO mail-yw0-f172.google.com) (209.85.161.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 24 Dec 2016 22:24:21 +0000 Received: by mail-yw0-f172.google.com with SMTP id t125so143646635ywc.1 for ; Sat, 24 Dec 2016 14:24:17 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to:cc; bh=01u70b42mHYj83BBru4hZGC1V+4RRb/TnTTSZk+ldFs=; b=BHHdj1X2tdf3sqHFQyMmqllrEY0Zs7lNvU+qbe+1fbKQLx7xD3IZoNzQTzPoou+yuY 1IJadrRlEgD+0ZIXahwgHrpIYHVhkFDBFMQMAuUdXXtzmWm1TsOhiFppUo9M/zpYzGW8 QK9FhRowAkMsAObWgQENBMMeUc65+fz1nUG9IXD2JZh7t9KsJpfI4+U9dG3aSIXlRLrU Up7HBIpPuimZCWC6XH4k5npnVBZtPHVW13vIFK2gXzOeXch+oqnYaZkW0dmFr9w6kcGD pcybKM/vwURHpq9suBAuUmQ0I9trDMUPAnz9zWjrpf03rky4jyptWRqv/MGgjHZrXAE1 OuyA== X-Gm-Message-State: AIkVDXIcd5M/GrC7uZc5OLpSJHBnMpuHqsLfKLL560oBK/459/9SL0cOibBCtjos8pQRhNuU6qZ6lqK0Cb06+l6n X-Received: by 10.129.163.69 with SMTP id a66mr17856222ywh.175.1482618255625; Sat, 24 Dec 2016 14:24:15 -0800 (PST) MIME-Version: 1.0 Received: by 10.129.92.4 with HTTP; Sat, 24 Dec 2016 14:24:15 -0800 (PST) From: Jim Wilson Date: Sat, 24 Dec 2016 14:24:15 -0800 Message-ID: Subject: [PATCH] aarch64 sim vector mul bug fix To: gdb-patches@sourceware.org Cc: Nick Clifton The vector mul instruction is doing a widening multiply, but isn't supposed to. mull does a widening multiply, mul does a regular multiply. The testcase works with the patch, and fails without the patch. GCC C testsuite failures drop from 2538 to 2473. Jim 2016-12-23 Jim Wilson sim/aarch64/ * simulator.c (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth args same size as third arg. sim/testsuite/sim/aarch64/ * mul.s: New. diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c index be3d6c7..9da12d3 100644 --- a/sim/aarch64/simulator.c +++ b/sim/aarch64/simulator.c @@ -3724,15 +3724,15 @@ do_vec_mul (sim_cpu *cpu) switch (INSTR (23, 22)) { case 0: - DO_VEC_WIDENING_MUL (full ? 16 : 8, uint16_t, u8, u16); + DO_VEC_WIDENING_MUL (full ? 16 : 8, uint8_t, u8, u8); return; case 1: - DO_VEC_WIDENING_MUL (full ? 8 : 4, uint32_t, u16, u32); + DO_VEC_WIDENING_MUL (full ? 8 : 4, uint16_t, u16, u16); return; case 2: - DO_VEC_WIDENING_MUL (full ? 4 : 2, uint64_t, u32, u64); + DO_VEC_WIDENING_MUL (full ? 4 : 2, uint32_t, u32, u32); return; case 3: diff --git a/sim/testsuite/sim/aarch64/mul.s b/sim/testsuite/sim/aarch64/mul.s new file mode 100644 index 0000000..783dba7 --- /dev/null +++ b/sim/testsuite/sim/aarch64/mul.s @@ -0,0 +1,99 @@ +# mach: aarch64 + +# Check the non-widening multiply vector instruction: mul. + +.include "testutils.inc" + + .data + .align 4 +input: + .word 0x04030201 + .word 0x08070605 + .word 0x0c0b0a09 + .word 0x100f0e0d +m8b: + .word 0x10090401 + .word 0x40312419 +m16b: + .word 0x10090401 + .word 0x40312419 + .word 0x90796451 + .word 0x00e1c4a9 +m4h: + .word 0x18090401 + .word 0x70313c19 +m8h: + .word 0x18090401 + .word 0x70313c19 + .word 0x0879b451 + .word 0xe0e16ca9 +m2s: + .word 0x140a0401 + .word 0xa46a3c19 +m4s: + .word 0x140a0401 + .word 0xa46a3c19 + .word 0xb52ab451 + .word 0x464b6ca9 + + start + adrp x0, input + ldr q0, [x0, #:lo12:input] + + mul v1.8b, v0.8b, v0.8b + mov x1, v1.d[0] + adrp x3, m8b + ldr x4, [x0, #:lo12:m8b] + cmp x1, x4 + bne .Lfailure + + mul v1.16b, v0.16b, v0.16b + mov x1, v1.d[0] + mov x2, v1.d[1] + adrp x3, m16b + ldr x4, [x0, #:lo12:m16b] + cmp x1, x4 + bne .Lfailure + ldr x5, [x0, #:lo12:m16b+8] + cmp x2, x5 + bne .Lfailure + + mul v1.4h, v0.4h, v0.4h + mov x1, v1.d[0] + adrp x3, m4h + ldr x4, [x0, #:lo12:m4h] + cmp x1, x4 + bne .Lfailure + + mul v1.8h, v0.8h, v0.8h + mov x1, v1.d[0] + mov x2, v1.d[1] + adrp x3, m8h + ldr x4, [x0, #:lo12:m8h] + cmp x1, x4 + bne .Lfailure + ldr x5, [x0, #:lo12:m8h+8] + cmp x2, x5 + bne .Lfailure + + mul v1.2s, v0.2s, v0.2s + mov x1, v1.d[0] + adrp x3, m2s + ldr x4, [x0, #:lo12:m2s] + cmp x1, x4 + bne .Lfailure + + mul v1.4s, v0.4s, v0.4s + mov x1, v1.d[0] + mov x2, v1.d[1] + adrp x3, m4s + ldr x4, [x0, #:lo12:m4s] + cmp x1, x4 + bne .Lfailure + ldr x5, [x0, #:lo12:m4s+8] + cmp x2, x5 + bne .Lfailure + + pass +.Lfailure: + fail