From patchwork Mon Jan 2 23:12:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 18767 Received: (qmail 105960 invoked by alias); 2 Jan 2017 23:12:47 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 105948 invoked by uid 89); 2 Jan 2017 23:12:47 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.3 required=5.0 tests=AWL, BAYES_20, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=no version=3.3.2 spammy=simulator, 0xFF, multiply, m4s X-HELO: mail-yw0-f169.google.com Received: from mail-yw0-f169.google.com (HELO mail-yw0-f169.google.com) (209.85.161.169) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 02 Jan 2017 23:12:37 +0000 Received: by mail-yw0-f169.google.com with SMTP id v81so174456299ywb.2 for ; Mon, 02 Jan 2017 15:12:36 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to:cc; bh=CH+TpXbdaXbVsTwET0UZ/yNlFEknuuNYmxPrDzngzvQ=; b=BZFJxRNoFB1MpMFIGhK/+8uIG8Z08QOK05acgUlL3alr00QJGxbRNyxC0sek9ChuJ1 pwR0K4t3/2UrMS4DRcQS1kQKPk7N5G01koarD5+UQgxF5Lk+/qz929XHw+ntzDdqshZN WYyoH2yDoe2XOoVw9FQbPmXCwb85V/KCU247PsH4mxtr5yZeSaqaPnFPiCIwBwtncowa 1hMniMqLDPmGLAWewHWBYCW7zgQi2+xpciOC/7ZsuYzc99LYbGH4Q4Q6WcLouQQuldf3 llzFY5SJejs4hjq0DSO5/IgL7zNeGPI3KQRV3BDRKIJE5+0xW2hRVph+UZ+q5j6OrHuU SaJw== X-Gm-Message-State: AIkVDXLJBXMMa5eWIAO/i2FIaTx54Rd7y8yzhiBGkjmU54cAOLcl8Pm/tgbb/Fqiv1Pfvnl/yfF2S0RwUAQx49RA X-Received: by 10.129.4.130 with SMTP id 124mr54099070ywe.333.1483398755393; Mon, 02 Jan 2017 15:12:35 -0800 (PST) MIME-Version: 1.0 Received: by 10.129.92.4 with HTTP; Mon, 2 Jan 2017 15:12:35 -0800 (PST) From: Jim Wilson Date: Mon, 2 Jan 2017 15:12:35 -0800 Message-ID: Subject: [PATCH] aarch64 sim mls and movi bug fixes To: gdb-patches@sourceware.org Cc: Nick Clifton The mls instruction computes accumulator - product, but the simulator accidentally has the subtract operands swapped. While writing the testcase for this problem, I discovered that the movi instruction is broken, there is a missing break after the half word support. Both are simple fixes. The testcase works with the patch, and fails without the patch. The mls fix takes GCC C testsuite failures from 2407 to 2406, and the movi fix then takes it from 2406 to 2295. Jim sim/aarch64/ * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break. (do_vec_MLS): Reverse order of subtraction operands. sim/testsuite/sim/aarch64/ * mls.s: New. diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c index be3d6c7..65a0e2e 100644 --- a/sim/aarch64/simulator.c +++ b/sim/aarch64/simulator.c @@ -3221,7 +3221,8 @@ do_vec_MOV_immediate (sim_cpu *cpu) case 0x8: /* 16-bit, no shift. */ for (i = 0; i < (full ? 8 : 4); i++) aarch64_set_vec_u16 (cpu, vd, i, val); - /* Fall through. */ + break; + case 0xd: /* 32-bit, mask shift by 16. */ val <<= 8; val |= 0xFF; @@ -6346,25 +6347,25 @@ do_vec_MLS (sim_cpu *cpu) case 0: for (i = 0; i < (full ? 16 : 8); i++) aarch64_set_vec_u8 (cpu, vd, i, - (aarch64_get_vec_u8 (cpu, vn, i) - * aarch64_get_vec_u8 (cpu, vm, i)) - - aarch64_get_vec_u8 (cpu, vd, i)); + aarch64_get_vec_u8 (cpu, vd, i) + - (aarch64_get_vec_u8 (cpu, vn, i) + * aarch64_get_vec_u8 (cpu, vm, i))); return; case 1: for (i = 0; i < (full ? 8 : 4); i++) aarch64_set_vec_u16 (cpu, vd, i, - (aarch64_get_vec_u16 (cpu, vn, i) - * aarch64_get_vec_u16 (cpu, vm, i)) - - aarch64_get_vec_u16 (cpu, vd, i)); + aarch64_get_vec_u16 (cpu, vd, i) + - (aarch64_get_vec_u16 (cpu, vn, i) + * aarch64_get_vec_u16 (cpu, vm, i))); return; case 2: for (i = 0; i < (full ? 4 : 2); i++) aarch64_set_vec_u32 (cpu, vd, i, - (aarch64_get_vec_u32 (cpu, vn, i) - * aarch64_get_vec_u32 (cpu, vm, i)) - - aarch64_get_vec_u32 (cpu, vd, i)); + aarch64_get_vec_u32 (cpu, vd, i) + - (aarch64_get_vec_u32 (cpu, vn, i) + * aarch64_get_vec_u32 (cpu, vm, i))); return; default: diff --git a/sim/testsuite/sim/aarch64/mls.s b/sim/testsuite/sim/aarch64/mls.s new file mode 100644 index 0000000..a34a1aa --- /dev/null +++ b/sim/testsuite/sim/aarch64/mls.s @@ -0,0 +1,103 @@ +# mach: aarch64 + +# Check the vector multiply subtract instruction: mls. + +.include "testutils.inc" + +input: + .word 0x04030201 + .word 0x08070605 + .word 0x0c0b0a09 + .word 0x100f0e0d +m8b: + .word 0xf1f8fd00 + .word 0xc1d0dde8 +m16b: + .word 0xf1f8fd00 + .word 0xc1d0dde8 + .word 0x71889db0 + .word 0x01203d58 +m4h: + .word 0xe7f8fc00 + .word 0x8fd0c3e8 +m8h: + .word 0xe7f8fc00 + .word 0x8fd0c3e8 + .word 0xf7884bb0 + .word 0x1f209358 +m2s: + .word 0xebf5fc00 + .word 0x5b95c3e8 +m4s: + .word 0xebf5fc00 + .word 0x5b95c3e8 + .word 0x4ad54bb0 + .word 0xb9b49358 + + start + adrp x0, input + ldr q0, [x0, #:lo12:input] + + movi v1.8b, #1 + mls v1.8b, v0.8b, v0.8b + mov x1, v1.d[0] + adrp x3, m8b + ldr x4, [x3, #:lo12:m8b] + cmp x1, x4 + bne .Lfailure + + movi v1.16b, #1 + mls v1.16b, v0.16b, v0.16b + mov x1, v1.d[0] + mov x2, v1.d[1] + adrp x3, m16b + ldr x4, [x3, #:lo12:m16b] + cmp x1, x4 + bne .Lfailure + ldr x5, [x3, #:lo12:m16b+8] + cmp x2, x5 + bne .Lfailure + + movi v1.4h, #1 + mls v1.4h, v0.4h, v0.4h + mov x1, v1.d[0] + adrp x3, m4h + ldr x4, [x3, #:lo12:m4h] + cmp x1, x4 + bne .Lfailure + + movi v1.8h, #1 + mls v1.8h, v0.8h, v0.8h + mov x1, v1.d[0] + mov x2, v1.d[1] + adrp x3, m8h + ldr x4, [x3, #:lo12:m8h] + cmp x1, x4 + bne .Lfailure + ldr x5, [x3, #:lo12:m8h+8] + cmp x2, x5 + bne .Lfailure + + movi v1.2s, #1 + mls v1.2s, v0.2s, v0.2s + mov x1, v1.d[0] + adrp x3, m2s + ldr x4, [x3, #:lo12:m2s] + cmp x1, x4 + bne .Lfailure + + movi v1.4s, #1 + mls v1.4s, v0.4s, v0.4s + mov x1, v1.d[0] + mov x2, v1.d[1] + adrp x3, m4s + ldr x4, [x3, #:lo12:m4s] + cmp x1, x4 + bne .Lfailure + ldr x5, [x3, #:lo12:m4s+8] + cmp x2, x5 + bne .Lfailure + + pass +.Lfailure: + fail