From patchwork Fri Dec 2 04:49:25 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 18119 Received: (qmail 97255 invoked by alias); 2 Dec 2016 04:49:42 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 97229 invoked by uid 89); 2 Dec 2016 04:49:39 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-yw0-f171.google.com Received: from mail-yw0-f171.google.com (HELO mail-yw0-f171.google.com) (209.85.161.171) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 02 Dec 2016 04:49:27 +0000 Received: by mail-yw0-f171.google.com with SMTP id i145so212842531ywg.2 for ; Thu, 01 Dec 2016 20:49:27 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:from:date:message-id:subject:to:cc; bh=HL2YPsJbR5n5m14YGXShR3vxeyu7ya0PKezc/wj2DVU=; b=XoPbF7dZsG8oDijovIOUaJ3F8CIwpJ7V5A+02cQFHhsSIvCou8ervQSGJBSaAnMlsE Y7tR9DfQRtBOakXRBs7cKNDPejUXLj1Do3xraEOaKQBSCsKaT4JkBHunPl+vjVNXx8IE djSpjze/137AWgN5aAXAEpqE1DC5TvGvuML68UZWMVcavA17s95vCDgNRzU0Q4sjRsgM Wsa6KhARHscuMLniDuxT+427vUXSxVxqHt19pBNkwqPzcY03/OlLqc4CD63PsyqOU7Gf pL8dIF2H1955JY89Any3SxvqZBygYgD2NuXIg9jfPJAOxMFfPBQvHwUVwKhnz2hQPmSn IfNA== X-Gm-Message-State: AKaTC012lj5RwHingZmVt8Ja7uaRQbRgK1NhtE2/aA+Z4ct9Xpp5IrixiqxNsfyO2Dn/9xG01/p8CkPcHZnw4N5S X-Received: by 10.129.4.130 with SMTP id 124mr42859252ywe.333.1480654166345; Thu, 01 Dec 2016 20:49:26 -0800 (PST) MIME-Version: 1.0 Received: by 10.129.92.4 with HTTP; Thu, 1 Dec 2016 20:49:25 -0800 (PST) From: Jim Wilson Date: Thu, 1 Dec 2016 20:49:25 -0800 Message-ID: Subject: [PATCH] fix for aarch64 sim tbnz bug To: gdb-patches@sourceware.org Cc: Nick Clifton Debugged another gcc testsuite failure, and found that tbnz/tbz are broken when the bit position to test is greater than 31. There are two problems. The high bit of the bit position is shifted left by the wrong amount. And we need to use (uint64_t)1 to get a 64-bit shift result. Tested with a gcc C testsuite run. This reduces failures from 2856 to 2710. Jim sim/aarch64 * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting. (dexTestBranchImmediate): Shift high bit of pos by 5 not 4. diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c index 4fa5dc1..34fd17d 100644 --- a/sim/aarch64/simulator.c +++ b/sim/aarch64/simulator.c @@ -13353,7 +13353,7 @@ tbnz (sim_cpu *cpu, uint32_t pos, int32_t offset) unsigned rt = INSTR (4, 0); TRACE_DECODE (cpu, "emulated at line %d", __LINE__); - if (aarch64_get_reg_u64 (cpu, rt, NO_SP) & (1 << pos)) + if (aarch64_get_reg_u64 (cpu, rt, NO_SP) & (((uint64_t) 1) << pos)) aarch64_set_next_PC_by_offset (cpu, offset); } @@ -13364,7 +13364,7 @@ tbz (sim_cpu *cpu, uint32_t pos, int32_t offset) unsigned rt = INSTR (4, 0); TRACE_DECODE (cpu, "emulated at line %d", __LINE__); - if (!(aarch64_get_reg_u64 (cpu, rt, NO_SP) & (1 << pos))) + if (!(aarch64_get_reg_u64 (cpu, rt, NO_SP) & (((uint64_t) 1) << pos))) aarch64_set_next_PC_by_offset (cpu, offset); } @@ -13407,7 +13407,7 @@ dexTestBranchImmediate (sim_cpu *cpu) instr[18,5] = simm14 : signed offset counted in words instr[4,0] = uimm5 */ - uint32_t pos = ((INSTR (31, 31) << 4) | INSTR (23, 19)); + uint32_t pos = ((INSTR (31, 31) << 5) | INSTR (23, 19)); int32_t offset = simm32 (aarch64_get_instr (cpu), 18, 5) << 2; NYI_assert (30, 25, 0x1b);