diff mbox

aarch64 sim big-endian support

Message ID CABXYE2UfwrSxRADdgFRuBJzTM-1_DPaP5LJSULSQ-808X8dccQ@mail.gmail.com
State New, archived
Headers

Commit Message

Jim Wilson June 3, 2016, 2:36 a.m. UTC 
  On aarch64, code is always little-endian, even when compiling
big-endian, so we need to force little-endian when reading
instructions.

Running the gcc C language testsuite, I get for an aarch64-elf target

# of expected passes            35433
# of unexpected failures        254
# of unsupported tests          131

and for an aarch64_be-elf target with the attached patch I get

# of expected passes            35200
# of unexpected failures        487
# of unsupported tests          131

so this simple patch gets us most of the way there.  I haven't tried
looking at the other problems yet.

I also have a dejagnu patch I wrote to make this work, which I will be
submitting to the dejagnu team shortly.

Jim

Comments

Jim Wilson June 10, 2016, 4:24 p.m. UTC | #1 
ping

for the attachment, see
https://sourceware.org/ml/gdb-patches/2016-06/msg00046.html

On Thu, Jun 2, 2016 at 7:36 PM, Jim Wilson <jim.wilson@linaro.org> wrote:
> On aarch64, code is always little-endian, even when compiling
> big-endian, so we need to force little-endian when reading
> instructions.
>
> Running the gcc C language testsuite, I get for an aarch64-elf target
>
> # of expected passes            35433
> # of unexpected failures        254
> # of unsupported tests          131
>
> and for an aarch64_be-elf target with the attached patch I get
>
> # of expected passes            35200
> # of unexpected failures        487
> # of unsupported tests          131
>
> so this simple patch gets us most of the way there.  I haven't tried
> looking at the other problems yet.
>
> I also have a dejagnu patch I wrote to make this work, which I will be
> submitting to the dejagnu team shortly.
>
> Jim
Mike Frysinger June 10, 2016, 6:06 p.m. UTC | #2 
On 02 Jun 2016 19:36, Jim Wilson wrote:
>  aarch64_step (sim_cpu *cpu)
>  {
>    uint64_t pc = aarch64_get_PC (cpu);
> +  enum bfd_endian saved_target_byte_order;
>  
>    if (pc == TOP_LEVEL_RETURN_PC)
>      return FALSE;
>  
>    aarch64_set_next_PC (cpu, pc + 4);
> +
> +  /* Code is always little-endian.  */
> +  saved_target_byte_order = current_target_byte_order;
> +  current_target_byte_order = BFD_ENDIAN_LITTLE;
>    aarch64_get_instr (cpu) = aarch64_get_mem_u32 (cpu, pc);
> +  current_target_byte_order = saved_target_byte_order;

i don't think you should be messing with global state.  the sim core
has functions for reading raw opcodes if that's what you need.
-mike
diff mbox

Patch

2016-06-02  Jim Wilson  <jim.wilson@linaro.org>

	sim/aarch64/
	* simulator.c (aarch64_step): New var saved_target_byte_order.  Force
	byte order to BFD_ENDIAN_LITTLE before pc read, then restore saved
	value.

diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c
index 88cb03d..5a1814c 100644
--- a/sim/aarch64/simulator.c
+++ b/sim/aarch64/simulator.c
@@ -14078,12 +14078,18 @@  static bfd_boolean
 aarch64_step (sim_cpu *cpu)
 {
   uint64_t pc = aarch64_get_PC (cpu);
+  enum bfd_endian saved_target_byte_order;
 
   if (pc == TOP_LEVEL_RETURN_PC)
     return FALSE;
 
   aarch64_set_next_PC (cpu, pc + 4);
+
+  /* Code is always little-endian.  */
+  saved_target_byte_order = current_target_byte_order;
+  current_target_byte_order = BFD_ENDIAN_LITTLE;
   aarch64_get_instr (cpu) = aarch64_get_mem_u32 (cpu, pc);
+  current_target_byte_order = saved_target_byte_order;
 
   TRACE_INSN (cpu, " pc = %" PRIx64 " instr = %08x", pc,
 	      aarch64_get_instr (cpu));