From patchwork Sun Feb 5 02:03:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 19116 Received: (qmail 78651 invoked by alias); 5 Feb 2017 02:03:24 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 78634 invoked by uid 89); 5 Feb 2017 02:03:23 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.4 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=no version=3.3.2 spammy=1037, 1590, Hx-languages-length:3462, bif X-HELO: mail-yw0-f177.google.com Received: from mail-yw0-f177.google.com (HELO mail-yw0-f177.google.com) (209.85.161.177) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sun, 05 Feb 2017 02:03:13 +0000 Received: by mail-yw0-f177.google.com with SMTP id u68so32687921ywg.0 for ; Sat, 04 Feb 2017 18:03:12 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to:cc; bh=3wIcV0zfkclj7wYfJ/3ICAmVsMxUPSFQtsO9op0meBk=; b=TPclDzZ9xJPsPYmM0C0GpDFSEghICnYgq5Y/glIvZ4OT7Cr6nUTDhCSLcQjIW9kcTh aEzwmZO+GHKXGKAMKpa16emru5O758cLBgzRhQNjP/2NvG9jrendMcUeo7Lx4EawP90P pgBO66remcph9rgCQqIUOy5ItRdqo0/zAWmPszqdR/Z20LRKeMWPH2yJJC+onjVOfj5z 7/Yc2DOkku6TXpJXgCnbeP5qiikOW9KLLo5PVEJCwbUz9K4EqLyoz8ZNrJYH/BZwEtg2 77mByjWZoQ9aO8SEOkyvVJBwqwJJL3tsu8kOqJwqU66p0HP8bp50zr5ZYDsO21g62OqQ 0+8w== X-Gm-Message-State: AIkVDXKTZX8hoDMOt/wgPunieSoXBonnFgcznhQxL723fqBtQo65iEJr30B6Ek4ahAryXC39zI5/4fDC5P5rlo7l X-Received: by 10.129.181.81 with SMTP id c17mr2591279ywk.265.1486260191321; Sat, 04 Feb 2017 18:03:11 -0800 (PST) MIME-Version: 1.0 Received: by 10.129.37.1 with HTTP; Sat, 4 Feb 2017 18:03:10 -0800 (PST) From: Jim Wilson Date: Sat, 4 Feb 2017 18:03:10 -0800 Message-ID: Subject: [PATCH] aarch64 sim bit/bif bug fix To: gdb-patches@sourceware.org Cc: Nick Clifton This fixes the bit and bif instructions. The code is using u32 set/get, but 16/8 loop bounds, which gives out of range errors. Also, it is computing the value wrong, as it is a bitwise operation, not an operation checking byte/word values for zero/non-zero. I rewrote the code a little to make the operation more obvious. It now looks more like bsl which is a closely related instruction. The testcase fails without the patch and works with the patch. GCC C testsuite failures drop from 1701 to 1590 (-111). Jim sim/aarch64/ * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and 2. Move test_false if inside loop. Fix logic for computing result stored to vd. sim/testsuite/sim/aarch64 * bit.s: New. diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c index a44e70a..13a2b1f 100644 --- a/sim/aarch64/simulator.c +++ b/sim/aarch64/simulator.c @@ -4085,17 +4085,17 @@ do_vec_bit (sim_cpu *cpu) NYI_assert (15, 10, 0x07); TRACE_DECODE (cpu, "emulated at line %d", __LINE__); - if (test_false) - { - for (i = 0; i < (full ? 16 : 8); i++) - if (aarch64_get_vec_u32 (cpu, vn, i) == 0) - aarch64_set_vec_u32 (cpu, vd, i, aarch64_get_vec_u32 (cpu, vm, i)); - } - else + for (i = 0; i < (full ? 4 : 2); i++) { - for (i = 0; i < (full ? 16 : 8); i++) - if (aarch64_get_vec_u32 (cpu, vn, i) != 0) - aarch64_set_vec_u32 (cpu, vd, i, aarch64_get_vec_u32 (cpu, vm, i)); + uint32_t vd_val = aarch64_get_vec_u32 (cpu, vd, i); + uint32_t vn_val = aarch64_get_vec_u32 (cpu, vn, i); + uint32_t vm_val = aarch64_get_vec_u32 (cpu, vm, i); + if (test_false) + aarch64_set_vec_u32 (cpu, vd, i, + (vd_val & vm_val) | (vn_val & ~vm_val)); + else + aarch64_set_vec_u32 (cpu, vd, i, + (vd_val & ~vm_val) | (vn_val & vm_val)); } } diff --git a/sim/testsuite/sim/aarch64/bit.s b/sim/testsuite/sim/aarch64/bit.s new file mode 100644 index 0000000..650d317 --- /dev/null +++ b/sim/testsuite/sim/aarch64/bit.s @@ -0,0 +1,91 @@ +# mach: aarch64 + +# Check the bitwise vector instructions: bif, bit, bsl, eor. + +.include "testutils.inc" + + .data + .align 4 +inputa: + .word 0x04030201 + .word 0x08070605 + .word 0x0c0b0a09 + .word 0x100f0e0d +inputb: + .word 0x40302010 + .word 0x80706050 + .word 0xc0b0a090 + .word 0x01f0e0d0 +mask: + .word 0xFF00FF00 + .word 0x00FF00FF + .word 0xF0F0F0F0 + .word 0x0F0F0F0F + + start + adrp x0, inputa + ldr q0, [x0, #:lo12:inputa] + adrp x0, inputb + ldr q1, [x0, #:lo12:inputb] + adrp x0, mask + ldr q2, [x0, #:lo12:mask] + + mov v3.8b, v0.8b + bif v3.8b, v1.8b, v2.8b + addv b4, v3.8b + mov x1, v4.d[0] + cmp x1, #306 + bne .Lfailure + + mov v3.16b, v0.16b + bif v3.16b, v1.16b, v2.16b + addv b4, v3.16b + mov x1, v4.d[0] + cmp x1, #1020 + bne .Lfailure + + mov v3.8b, v0.8b + bit v3.8b, v1.8b, v2.8b + addv b4, v3.8b + mov x1, v4.d[0] + cmp x1, #306 + bne .Lfailure + + mov v3.16b, v0.16b + bit v3.16b, v1.16b, v2.16b + addv b4, v3.16b + mov x1, v4.d[0] + cmp x1, #1037 + bne .Lfailure + + mov v3.8b, v2.8b + bsl v3.8b, v0.8b, v1.8b + addv b4, v3.8b + mov x1, v4.d[0] + cmp x1, #306 + bne .Lfailure + + mov v3.16b, v2.16b + bsl v3.16b, v0.16b, v1.16b + addv b4, v3.16b + mov x1, v4.d[0] + cmp x1, #1020 + bne .Lfailure + + mov v3.8b, v0.8b + eor v3.8b, v1.8b, v2.8b + addv b4, v3.8b + mov x1, v4.d[0] + cmp x1, #1020 + bne .Lfailure + + mov v3.16b, v0.16b + eor v3.16b, v1.16b, v2.16b + addv b4, v3.16b + mov x1, v4.d[0] + cmp x1, #2039 + bne .Lfailure + + pass +.Lfailure: + fail