From patchwork Fri Apr 7 08:54:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Hayward X-Patchwork-Id: 19890 Received: (qmail 71787 invoked by alias); 7 Apr 2017 08:54:22 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 71750 invoked by uid 89); 7 Apr 2017 08:54:21 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.5 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: EUR01-HE1-obe.outbound.protection.outlook.com Received: from mail-he1eur01on0057.outbound.protection.outlook.com (HELO EUR01-HE1-obe.outbound.protection.outlook.com) (104.47.0.57) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 07 Apr 2017 08:54:19 +0000 Received: from AM3PR08MB0101.eurprd08.prod.outlook.com (10.160.211.19) by AM3PR08MB0102.eurprd08.prod.outlook.com (10.160.211.20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1019.17; Fri, 7 Apr 2017 08:54:17 +0000 Received: from AM3PR08MB0101.eurprd08.prod.outlook.com ([fe80::5931:f431:f97d:943d]) by AM3PR08MB0101.eurprd08.prod.outlook.com ([fe80::5931:f431:f97d:943d%16]) with mapi id 15.01.1005.022; Fri, 7 Apr 2017 08:54:17 +0000 From: Alan Hayward To: "gdb-patches@sourceware.org" CC: nd Subject: [PATCH] nds32: Abort instead of returning REG_UNKNOWN Date: Fri, 7 Apr 2017 08:54:17 +0000 Message-ID: authentication-results: sourceware.org; dkim=none (message not signed) header.d=none; sourceware.org; dmarc=none action=none header.from=arm.com; x-ms-exchange-messagesentrepresentingtype: 1 x-microsoft-exchange-diagnostics: 1; AM3PR08MB0102; 7:m6/uSvYNF/H7Fk6RkSZWUz0La5iEqIKwS1SU5btrRNcp5Z2BTcW6l9uwHsgYK6ujubX8xVSYBbdG5zJuwg7gUjw6DLeaadsUbTLjviUAhIPLB2FMNrjQ/MMyEtwKyU8dVRo7I+qS32Ug7HQd6MMWG7m4DbCwhkVwHkVp+QTs12Euu/IL331MMSZsVOKwzbjRkSOetETsVqrkDYM6VU+BjOHlwv8sLeRySTP0i/KLo7UXKPVEuIGwb3NFqjZR4AqQPO0CQJwsLcRSQ7Gv1Zv0JX3AZsiGds1f5Gzh+zbpR8yg9MKQ16O0bQAI+mhp8yPsNIdt2uXlrUgEPdal9h55rA== x-ms-office365-filtering-correlation-id: 6a6c933d-e4e0-4503-7d82-08d47d93ac9b x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001)(2017030254075)(48565401081)(201703131423075)(201703031133081)(201702281549075); SRVR:AM3PR08MB0102; nodisclaimer: True x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(180628864354917); x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040450)(601004)(2401047)(8121501046)(5005006)(93006095)(93001095)(10201501046)(3002001)(6055026)(6041248)(201703131423075)(201702281528075)(201703061421075)(20161123555025)(20161123560025)(20161123564025)(20161123562025)(6072148); SRVR:AM3PR08MB0102; BCL:0; PCL:0; RULEID:; SRVR:AM3PR08MB0102; x-forefront-prvs: 0270ED2845 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(6009001)(39840400002)(39450400003)(39860400002)(39400400002)(39410400002)(377424004)(305945005)(2501003)(2351001)(6916009)(2900100001)(36756003)(50986999)(3846002)(102836003)(6116002)(189998001)(54356999)(86362001)(110136004)(6486002)(6512007)(5660300001)(3660700001)(2906002)(25786009)(6436002)(8676002)(81166006)(33656002)(6506006)(5640700003)(99286003)(4326008)(3280700002)(53936002)(66066001)(8936002)(38730400002); DIR:OUT; SFP:1101; SCL:1; SRVR:AM3PR08MB0102; H:AM3PR08MB0101.eurprd08.prod.outlook.com; FPR:; SPF:None; MLV:sfv; LANG:en; spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-ID: MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Apr 2017 08:54:17.2566 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM3PR08MB0102 This patch is cut from "[PATCH] Remove MAX_REGISTER_SIZE from regcache.c" When reading/writing a pseudo register, instead of returning REG_UNKNOWN on an error, assert instead. This will make nds32 behave like all other architectures. This is required due to some regcache refactoring (see the "Remove MAX_REGISTER_SIZE from regcache.c" thread). Tested on a --enable-targets=all build using make check with board files unix and native-gdbserver. I do not have a nds32 machine to test on. Ok to commit? Alan. 2017-04-07 Alan Hayward * nds32-tdep.c (nds32_pseudo_register_read): Abort on errors. (nds32_pseudo_register_write): Likewise. /* Helper function for NDS32 ABI. Return true if FPRs can be used diff --git a/gdb/nds32-tdep.c b/gdb/nds32-tdep.c index 05c48aa27d84bc0286712f0143a9447a79ae066b..804a11fb27fb0625338f1e5cda338f133b6f119d 100644 --- a/gdb/nds32-tdep.c +++ b/gdb/nds32-tdep.c @@ -445,11 +445,12 @@ nds32_pseudo_register_read (struct gdbarch *gdbarch, struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); gdb_byte reg_buf[8]; int offset, fdr_regnum; - enum register_status status = REG_UNKNOWN; + enum register_status status; - /* Sanity check. */ - if (tdep->fpu_freg == -1 || tdep->use_pseudo_fsrs == 0) - return status; + /* This function is registered in nds32_gdbarch_init only after these are + set. */ + gdb_assert (tdep->fpu_freg != -1); + gdb_assert (tdep->use_pseudo_fsrs != 0); regnum -= gdbarch_num_regs (gdbarch); @@ -466,9 +467,11 @@ nds32_pseudo_register_read (struct gdbarch *gdbarch, status = regcache_raw_read (regcache, fdr_regnum, reg_buf); if (status == REG_VALID) memcpy (buf, reg_buf + offset, 4); + + return status; } - return status; + gdb_assert_not_reached ("invalid pseudo register number"); } /* Implement the "pseudo_register_write" gdbarch method. */ @@ -482,9 +485,10 @@ nds32_pseudo_register_write (struct gdbarch *gdbarch, gdb_byte reg_buf[8]; int offset, fdr_regnum; - /* Sanity check. */ - if (tdep->fpu_freg == -1 || tdep->use_pseudo_fsrs == 0) - return; + /* This function is registered in nds32_gdbarch_init only after these are + set. */ + gdb_assert (tdep->fpu_freg != -1); + gdb_assert (tdep->use_pseudo_fsrs != 0); regnum -= gdbarch_num_regs (gdbarch); @@ -501,7 +505,10 @@ nds32_pseudo_register_write (struct gdbarch *gdbarch, regcache_raw_read (regcache, fdr_regnum, reg_buf); memcpy (reg_buf + offset, buf, 4); regcache_raw_write (regcache, fdr_regnum, reg_buf); + return; } + + gdb_assert_not_reached ("invalid pseudo register number"); }