sim: riscv: Fix build issue due to recent binutils commit

Message ID AS8P193MB1285FF1BF62E4789273FFA1BE4E62@AS8P193MB1285.EURP193.PROD.OUTLOOK.COM
State New
Headers
Series sim: riscv: Fix build issue due to recent binutils commit |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_gdb_build--master-aarch64 fail Patch failed to apply
linaro-tcwg-bot/tcwg_gdb_build--master-arm fail Patch failed to apply

Commit Message

Bernd Edlinger May 9, 2024, 8:58 a.m. UTC
  The commit c144f6383379 removed INSN_CLASS_A and
added INSN_CLASS_ZAAMO and INSN_CLASS_ZALRSC instead,
which broke the build of the sim for riscv targets.

Fix that by using the new INSN_CLASS types.

Fixes: c144f6383379 ("RISC-V: Support B, Zaamo and Zalrsc extensions.")
---
 sim/riscv/sim-main.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
  

Comments

Tom Tromey May 9, 2024, 2:12 p.m. UTC | #1
>>>>> "Bernd" == Bernd Edlinger <bernd.edlinger@hotmail.de> writes:

Bernd> The commit c144f6383379 removed INSN_CLASS_A and
Bernd> added INSN_CLASS_ZAAMO and INSN_CLASS_ZALRSC instead,
Bernd> which broke the build of the sim for riscv targets.

Thanks for the patch.  I approved an identical one that showed up a bit
earlier in my mailbox.

Tom
  

Patch

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index d556e6f5bdd..8234a79d924 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -1386,7 +1386,8 @@  execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 
   switch (op->insn_class)
     {
-    case INSN_CLASS_A:
+    case INSN_CLASS_ZAAMO:
+    case INSN_CLASS_ZALRSC:
       /* Check whether model with A extension is selected.  */
       if (riscv_cpu->csr.misa & 1)
 	return execute_a (cpu, iw, op);