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Mon, 15 Apr 2024 08:39:23 +0000 Received: from AS8P193MB1285.EURP193.PROD.OUTLOOK.COM ([fe80::5403:f1ad:efaf:1f71]) by AS8P193MB1285.EURP193.PROD.OUTLOOK.COM ([fe80::5403:f1ad:efaf:1f71%4]) with mapi id 15.20.7452.049; Mon, 15 Apr 2024 08:39:23 +0000 Message-ID: Date: Mon, 15 Apr 2024 10:41:16 +0200 User-Agent: Mozilla Thunderbird Content-Language: en-US To: "gdb-patches@sourceware.org" , Andrew Burgess From: Bernd Edlinger Subject: [PATCH v3] sim: riscv: Fix some compatibility issues with gcc X-TMN: [+5hUVCyS8ljKlzCrP6EHBdf/fR/q5EZAuT9c5DlseNCoDUhLce2hIztAmRaFGmcM] X-ClientProxiedBy: FR3P281CA0147.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:95::10) To AS8P193MB1285.EURP193.PROD.OUTLOOK.COM (2603:10a6:20b:333::21) X-Microsoft-Original-Message-ID: <7d05d912-d2ca-4a11-8f89-97f1f262c43f@hotmail.de> MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AS8P193MB1285:EE_|AS8P193MB2287:EE_ X-MS-Office365-Filtering-Correlation-Id: c5aff17e-7b1d-410f-3486-08dc5d278d51 X-Microsoft-Antispam: BCL:0; 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Note that using the command line argument --architecture riscv:rv32 is not really working, because compile-time constants like WITH_TARGET_WORD_BITSIZE and architecture dependent types like unsigned_word are used everywhere. So change the riscv/acinclude.m4 to use the same logic here, and disable selecting non-working architectures per command line argument. The second issue is that gcc does by default generate instructions in INSN_CLASS_C, so move the M(GC) to top of list, in riscv/model_list.def. This changes the default cpu-model to include the class c instructions when no --model command line argument is used. With these changes a simple C-program can be executed, however there is still work to do, since when the program does floating point operations, gcc starts to generate hardware floating point instructions, with no obvious opt-out option. Note the gcc test suite can be used to test the simulator in this way: make check-gcc RUNTESTFLAGS="--target_board=multi-sim SIM=riscv-unknown-elf-run" Now many tests are passed, except those which use floating point instructions. To work around the not supported float instructions the following gcc configuration can be used, which makes most of the gcc test cases successfully executed: .../gcc-trunk/configure --prefix=... --target=riscv-unknown-elf --disable-multilib --with-arch=rv32imac --with-abi=ilp32 Note: binutils are installed at prefix path and newlib/libgloss in-tree. --- sim/configure | 6 +++--- sim/riscv/acinclude.m4 | 4 ++-- sim/riscv/machs.c | 2 +- sim/riscv/model_list.def | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) v2: updated the commit message, with some hints how to compile a compatible gcc toolchain. v3: addressed review commments, disable non-working --architecture command line options, split out the fix for class-c instructions. diff --git a/sim/configure b/sim/configure index 1ebef377973..fdc0a86d524 100755 --- a/sim/configure +++ b/sim/configure @@ -17479,10 +17479,10 @@ $as_echo "$sim_ppc_xor_endian" >&6; } { $as_echo "$as_me:${as_lineno-$LINENO}: checking riscv bitsize" >&5 $as_echo_n "checking riscv bitsize... " >&6; } -SIM_RISCV_BITSIZE=64 +SIM_RISCV_BITSIZE=32 case $target in #( - riscv32*) : - SIM_RISCV_BITSIZE=32 ;; #( + riscv64*) : + SIM_RISCV_BITSIZE=64 ;; #( *) : ;; esac diff --git a/sim/riscv/acinclude.m4 b/sim/riscv/acinclude.m4 index 0c6290c9c08..e9953c1017d 100644 --- a/sim/riscv/acinclude.m4 +++ b/sim/riscv/acinclude.m4 @@ -15,8 +15,8 @@ dnl along with this program. If not, see . dnl dnl NB: This file is included in sim/configure, so keep settings namespaced. AC_MSG_CHECKING([riscv bitsize]) -SIM_RISCV_BITSIZE=64 +SIM_RISCV_BITSIZE=32 AS_CASE([$target], - [riscv32*], [SIM_RISCV_BITSIZE=32]) + [riscv64*], [SIM_RISCV_BITSIZE=64]) AC_MSG_RESULT([$SIM_RISCV_BITSIZE]) AC_SUBST(SIM_RISCV_BITSIZE) diff --git a/sim/riscv/machs.c b/sim/riscv/machs.c index 77ae000e7a5..98b790e8a52 100644 --- a/sim/riscv/machs.c +++ b/sim/riscv/machs.c @@ -120,7 +120,7 @@ const SIM_MACH * const riscv_sim_machs[] = #if WITH_TARGET_WORD_BITSIZE >= 64 &rv64i_mach, #endif -#if WITH_TARGET_WORD_BITSIZE >= 32 +#if WITH_TARGET_WORD_BITSIZE == 32 &rv32i_mach, #endif NULL diff --git a/sim/riscv/model_list.def b/sim/riscv/model_list.def index b83557e5539..df9ec897126 100644 --- a/sim/riscv/model_list.def +++ b/sim/riscv/model_list.def @@ -1,9 +1,9 @@ +M(GC) M(G) M(I) M(IM) M(IMA) M(IA) -M(GC) M(IC) M(IMC) M(IMAC)