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[87.115.72.95]) by smtp.gmail.com with ESMTPSA id p9-20020a1c5449000000b003dc1d668866sm17565362wmi.10.2023.03.20.14.54.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Mar 2023 14:54:55 -0700 (PDT) To: Tom Tromey , Andrew Burgess via Gdb-patches Subject: [PATCHv2] gdb/riscv: add systemtap support In-Reply-To: <871qljduau.fsf@redhat.com> References: <87y1nrh729.fsf@tromey.com> <871qljduau.fsf@redhat.com> Date: Mon, 20 Mar 2023 21:54:54 +0000 Message-ID: <87v8ivcclt.fsf@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Andrew Burgess via Gdb-patches From: Andrew Burgess Reply-To: Andrew Burgess Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org Sender: "Gdb-patches" Here's a V2 with the changes in riscv-tdep.c rather than riscv-linux-tdep.c. Nothing else has changed. Thanks, Andrew Reviewed-By: Tom Tromey --- commit f0288ff3d6468fb6c42c69a027f391d3460f790b Author: Andrew Burgess Date: Sat Mar 18 15:15:49 2023 +0000 gdb/riscv: add systemtap support This commit is initial support for SystemTap for RISC-V Linux. The following two tests exercise SystemTap functionality, and are showing many failures, which are all fixed by this commit: gdb.cp/exceptprint.exp gdb.base/stap-probe.exp One thing I wasn't sure about is if the SystemTap support should be Linux specific, or architecture specific. For aarch64, arm, ia64, and ppc, the SystemTap support seems to libe in the ARCH-linux-tdep.c file, while for amd64, i386, and s390 the implementation lives in ARCH-tdep.c. I have no idea which of these is the better choice -- or maybe both choices are correct in the right circumstances, and I'm just not aware of how to choose between them. Anyway, for this patch I selected riscv-tdep.c (though clearly, moving the changes to riscv-linux-tdep.c is trivial if anyone thinks that's a more appropriate location). The stap-probe.exp file tests immediate, register, and register indirect operands, all of which appear to be working fine with this commit. The generic expression support doesn't appear to be architecture specific, so I'd expect that to work fine too. diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index 771d892df26..d01ba9bfa6a 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -56,6 +56,7 @@ #include "prologue-value.h" #include "arch/riscv.h" #include "riscv-ravenscar-thread.h" +#include "safe-ctype.h" /* The stack must be 16-byte aligned. */ #define SP_ALIGNMENT 16 @@ -4039,6 +4040,33 @@ riscv_gnu_triplet_regexp (struct gdbarch *gdbarch) return "riscv(32|64)?"; } +/* Implementation of `gdbarch_stap_is_single_operand', as defined in + gdbarch.h. */ + +static int +riscv_stap_is_single_operand (struct gdbarch *gdbarch, const char *s) +{ + return (ISDIGIT (*s) /* Literal number. */ + || *s == '(' /* Register indirection. */ + || ISALPHA (*s)); /* Register value. */ +} + +/* String that appears before a register name in a SystemTap register + indirect expression. */ + +static const char *const stap_register_indirection_prefixes[] = +{ + "(", nullptr +}; + +/* String that appears after a register name in a SystemTap register + indirect expression. */ + +static const char *const stap_register_indirection_suffixes[] = +{ + ")", nullptr +}; + /* Initialize the current architecture based on INFO. If possible, re-use an architecture from ARCHES, which is a list of architectures already created during this debugging session. @@ -4277,6 +4305,13 @@ riscv_gdbarch_init (struct gdbarch_info info, disassembler_options_riscv ()); set_gdbarch_disassembler_options (gdbarch, &riscv_disassembler_options); + /* SystemTap Support. */ + set_gdbarch_stap_is_single_operand (gdbarch, riscv_stap_is_single_operand); + set_gdbarch_stap_register_indirection_prefixes + (gdbarch, stap_register_indirection_prefixes); + set_gdbarch_stap_register_indirection_suffixes + (gdbarch, stap_register_indirection_suffixes); + /* Hook in OS ABI-specific overrides, if they have been registered. */ gdbarch_init_osabi (info, gdbarch);