From patchwork Mon Dec 14 16:39:40 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nick Clifton X-Patchwork-Id: 10001 Received: (qmail 99683 invoked by alias); 14 Dec 2015 16:39:46 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 99673 invoked by uid 89); 14 Dec 2015 16:39:45 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.1 required=5.0 tests=AWL, BAYES_05, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_PASS, T_RP_MATCHES_RCVD autolearn=no version=3.3.2 X-HELO: mx1.redhat.com Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Mon, 14 Dec 2015 16:39:44 +0000 Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) by mx1.redhat.com (Postfix) with ESMTPS id 5753414CAD9 for ; Mon, 14 Dec 2015 16:39:43 +0000 (UTC) Received: from littlehelper.redhat.com (vpn1-4-217.ams2.redhat.com [10.36.4.217]) by int-mx11.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id tBEGdfFE022927 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO) for ; Mon, 14 Dec 2015 11:39:42 -0500 From: Nick Clifton To: gdb-patches@sourceware.org Subject: RFA: AArch64 sim: Add support for the MRS instruction Date: Mon, 14 Dec 2015 16:39:40 +0000 Message-ID: <87oadtougj.fsf@redhat.com> MIME-Version: 1.0 Hi Guys, I would like permission to apply the patch below to the AArch64 sim. It adds basic support for the MRS instruction (move from system register). Currently only read access to the DCZID register is supported. This support is needed because the memset function in Newlib tests the DCZID register to see if it can use the DC ZVA instruction to zero large blocks of memory. Without a correct value for the DCZID register memset can run amok, writing values all over the address space and eventually ending up with a seg-fault. The patch reduces the number of unexpected failures in the gcc testsuite by about an order of magnitude... OK to apply ? Cheers Nick PS. I would be happy to be a maintainer for the AArch64 sim, if that is agreeable. sim/ChangeLog 2015-12-14 Nick Clifton * aarch64/simulator.c (system_get): New function. Provides read access to the dczid system register. (do_mrs): New function - implements the MRS instruction. (dexSystem): Call do_mrs for the MRS instruction. Halt on unimplemented system instructions. diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c index 31c054c..8f9990c 100644 --- a/sim/aarch64/simulator.c +++ b/sim/aarch64/simulator.c @@ -12783,6 +12783,44 @@ dexExcpnGen (sim_cpu *cpu) HALT_UNALLOC; } +/* Stub for accessing system registers. + We implement support for the DCZID register since this is used + by the C library's memset function. */ + +static uint64_t +system_get (sim_cpu * cpu, unsigned op0, unsigned op1, unsigned crn, + unsigned crm, unsigned op2) +{ + if (crn == 0 && op1 == 3 && crm == 0 && op2 == 7) + /* DCZID_EL0 - the Data Cache Zero ID register. + We do not support DC ZVA at the moment, so + we return a value with the disable bit set. */ + return ((uint64_t) 1) << 4; + + HALT_NYI; +} + +static void +do_mrs (sim_cpu * cpu) +{ + /* instr[31:20] = 1101 01010 0011 + instr[19] = op0 + instr[18,16] = op1 + instr[15,12] = CRn + instr[11,8] = CRm + instr[7,5] = op2 + instr[4,0] = Rt */ + unsigned sys_op0 = uimm (aarch64_get_instr (cpu), 19, 19) + 2; + unsigned sys_op1 = uimm (aarch64_get_instr (cpu), 18, 16); + unsigned sys_crn = uimm (aarch64_get_instr (cpu), 15, 12); + unsigned sys_crm = uimm (aarch64_get_instr (cpu), 11, 8); + unsigned sys_op2 = uimm (aarch64_get_instr (cpu), 7, 5); + unsigned rt = uimm (aarch64_get_instr (cpu), 4, 0); + + aarch64_set_reg_u64 (cpu, rt, NO_SP, + system_get (cpu, sys_op0, sys_op1, sys_crn, sys_crm, sys_op2)); +} + static void dexSystem (sim_cpu *cpu) { @@ -12842,9 +12880,7 @@ dexSystem (sim_cpu *cpu) switch (op2) { - case 2: - HALT_NYI; - + case 2: HALT_NYI; case 4: dsb (cpu); return; case 5: dmb (cpu); return; case 6: isb (cpu); return; @@ -12855,25 +12891,26 @@ dexSystem (sim_cpu *cpu) case 0x3B0: /* MRS Wt, sys-reg. */ - /* FIXME: Ignore for now. */ + do_mrs (cpu); return; case 0x3B4: case 0x3BD: /* MRS Xt, sys-reg. */ - /* FIXME: Ignore for now. */ + do_mrs (cpu); return; case 0x0B7: /* DC , x. */ - /* FIXME: Ignore for now. */ + HALT_NYI; return; default: + /* if (uimm (aarch64_get_instr (cpu), 21, 20) == 0x1) - /* MSR , . */ - return; + do_msr (cpu); */ HALT_NYI; + return; } }