diff mbox

Recognize branch instruction on MIPS in gdb.trace/entry-values.exp

Message ID 87fvbmszkv.fsf@codesourcery.com
State New, archived
Headers

Commit Message

Yao Qi Jan. 8, 2015, 3:47 a.m. UTC 
  "Maciej W. Rozycki" <macro@linux-mips.org> writes:

>  Fair enough, the pattern matches more than necessary, but there are no 
> MIPS instructions it would match that it shouldn't, so let's keep your 
> proposal as it is for simplicity.  I have no further concerns, thanks for 
> your work and for getting through this review.

Patch below is what I pushed in.  Thanks for your review, Maciej.
diff mbox

Patch

diff --git a/gdb/testsuite/ChangeLog b/gdb/testsuite/ChangeLog
index 862f27c..2154036 100644
--- a/gdb/testsuite/ChangeLog
+++ b/gdb/testsuite/ChangeLog
@@ -1,3 +1,7 @@ 
+2015-01-08  Yao Qi  <yao@codesourcery.com>
+
+	* gdb.trace/entry-values.exp: Set call_insn for MIPS target.
+
 2015-01-07  Jan Kratochvil  <jan.kratochvil@redhat.com>
 
 	Fix testcase compilation.
diff --git a/gdb/testsuite/gdb.trace/entry-values.exp b/gdb/testsuite/gdb.trace/entry-values.exp
index e812241..2548e89 100644
--- a/gdb/testsuite/gdb.trace/entry-values.exp
+++ b/gdb/testsuite/gdb.trace/entry-values.exp
@@ -43,6 +43,20 @@  if { [istarget "arm*-*-*"] || [istarget "aarch64*-*-*"] } {
     set call_insn "brasl"
 } elseif { [istarget "powerpc*-*-*"] } {
     set call_insn "bl"
+} elseif { [istarget "mips*-*-*"] } {
+    # Skip the delay slot after the instruction used to make a call
+    # (which can be a jump or a branch) if it has one.
+    #
+    #  JUMP (or BRANCH) foo
+    #  insn1
+    #  insn2
+    #
+    # Most MIPS instructions used to make calls have a delay slot.
+    # These include JAL, JALS, JALX, JALR, JALRS, BAL and BALS.
+    # In this case the program continues from `insn2' when `foo'
+    # returns.  The only exception is JALRC, in which case execution
+    # resumes from `insn1' instead.
+    set call_insn {jalrc|[jb]al[sxr]*[ \t][^\r\n]+\r\n}
 } else {
     set call_insn "call"
 }