From patchwork Fri Mar 18 14:44:16 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nick Clifton X-Patchwork-Id: 11379 Received: (qmail 73683 invoked by alias); 18 Mar 2016 14:44:26 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 73597 invoked by uid 89); 18 Mar 2016 14:44:25 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RP_MATCHES_RCVD, SPF_HELO_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mx1.redhat.com Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Fri, 18 Mar 2016 14:44:20 +0000 Received: from int-mx14.intmail.prod.int.phx2.redhat.com (int-mx14.intmail.prod.int.phx2.redhat.com [10.5.11.27]) by mx1.redhat.com (Postfix) with ESMTPS id 3BC8F7AE94 for ; Fri, 18 Mar 2016 14:44:18 +0000 (UTC) Received: from littlehelper.redhat.com (vpn1-5-23.ams2.redhat.com [10.36.5.23]) by int-mx14.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u2IEiGbF025418 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO) for ; Fri, 18 Mar 2016 10:44:17 -0400 From: Nick Clifton To: gdb-patches@sourceware.org Subject: Commit: AArch64 sim: Fix off by one error checking for invalid vector array element Date: Fri, 18 Mar 2016 14:44:16 +0000 Message-ID: <87fuvnu9q7.fsf@redhat.com> MIME-Version: 1.0 Hi Guys, I am checking in the patch below to fix an off-by-one error pointed out by Mike Frysinger in my previous delta to the AArch64 simulator's vector register get and set functions. Cheers Nick sim/aarch64/ChangeLog 2016-03-18 Nick Clifton * cpustate.c (GET_VEC_ELEMENT): Fix off by one error checking for an invalid element index. (SET_VEC_ELEMENT): Likewise. diff --git a/sim/aarch64/cpustate.c b/sim/aarch64/cpustate.c index 86b1b15..19f485e 100644 --- a/sim/aarch64/cpustate.c +++ b/sim/aarch64/cpustate.c @@ -345,7 +345,7 @@ aarch64_set_FP_long_double (sim_cpu *cpu, VReg reg, FRegister a) #define GET_VEC_ELEMENT(REG, ELEMENT, FIELD) \ do \ { \ - if (element > ARRAY_SIZE (cpu->fr[0].FIELD)) \ + if (element >= ARRAY_SIZE (cpu->fr[0].FIELD)) \ { \ TRACE_REGISTER (cpu, \ "Internal SIM error: invalid element number: %d ",\ @@ -421,7 +421,7 @@ aarch64_get_vec_double (sim_cpu *cpu, VReg reg, unsigned element) #define SET_VEC_ELEMENT(REG, ELEMENT, VAL, FIELD, PRINTER) \ do \ { \ - if (ELEMENT > ARRAY_SIZE (cpu->fr[0].FIELD)) \ + if (ELEMENT >= ARRAY_SIZE (cpu->fr[0].FIELD)) \ { \ TRACE_REGISTER (cpu, \ "Internal SIM error: invalid element number: %d ",\