From patchwork Mon Nov 9 16:07:23 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nick Clifton X-Patchwork-Id: 9613 Received: (qmail 92902 invoked by alias); 9 Nov 2015 16:07:28 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 92890 invoked by uid 89); 9 Nov 2015 16:07:28 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL, BAYES_40, RP_MATCHES_RCVD, SPF_HELO_PASS autolearn=ham version=3.3.2 X-HELO: mx1.redhat.com Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Mon, 09 Nov 2015 16:07:27 +0000 Received: from int-mx13.intmail.prod.int.phx2.redhat.com (int-mx13.intmail.prod.int.phx2.redhat.com [10.5.11.26]) by mx1.redhat.com (Postfix) with ESMTPS id 19FC619CF9C for ; Mon, 9 Nov 2015 16:07:26 +0000 (UTC) Received: from littlehelper.redhat.com (vpn1-5-165.ams2.redhat.com [10.36.5.165]) by int-mx13.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id tA9G7O05007599 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Mon, 9 Nov 2015 11:07:25 -0500 From: Nick Clifton To: dj@redhat.com Cc: gdb-patches@sourceware.org Subject: RFA: RX sim: Add support for new operand types. Date: Mon, 09 Nov 2015 16:07:23 +0000 Message-ID: <878u67dumc.fsf@redhat.com> MIME-Version: 1.0 Hi DJ, A couple of recent patches to the RX disassembler have created some new operand types. Unfortunately I forgot to add these types to the RX simulator, which consequently broke. So here is a patch to add them. OK to apply ? Cheers Nick sim/rx/ChangeLog 2015-11-09 Nick Clifton * rx.c (id_names): Add nop4, nop5, nop6 and nop7. (decode_opcode): Likewise. (get_op): Handle RX_Operand_Zero_Indirect. Handle RX_Bad_Size and RX_MAX_SIZE. (put_op): Likewise. diff --git a/sim/rx/rx.c b/sim/rx/rx.c index 31c1443..a4768f9 100644 --- a/sim/rx/rx.c +++ b/sim/rx/rx.c @@ -80,6 +80,10 @@ static const char * id_names[] = { "RXO_nop", "RXO_nop2", "RXO_nop3", + "RXO_nop4", + "RXO_nop5", + "RXO_nop6", + "RXO_nop7", "RXO_scmpu", "RXO_smovu", @@ -406,6 +410,7 @@ get_op (const RX_Opcode_Decoded *rd, int i) put_reg (o->reg, get_reg (o->reg) - size2bytes[o->size]); /* fall through */ case RX_Operand_Postinc: /* [Rn+] */ + case RX_Operand_Zero_Indirect: /* [Rn + 0] */ case RX_Operand_Indirect: /* [Rn + addend] */ case RX_Operand_TwoReg: /* [Rn + scale * R2] */ #ifdef CYCLE_ACCURATE @@ -433,6 +438,7 @@ get_op (const RX_Opcode_Decoded *rd, int i) switch (o->size) { + default: case RX_AnySize: rx_abort (); @@ -473,6 +479,7 @@ get_op (const RX_Opcode_Decoded *rd, int i) to the size. */ switch (o->size) { + default: case RX_AnySize: rx_abort (); @@ -518,6 +525,7 @@ put_op (const RX_Opcode_Decoded *rd, int i, int v) switch (o->size) { + default: case RX_AnySize: if (o->type != RX_Operand_Register) rx_abort (); @@ -574,6 +582,7 @@ put_op (const RX_Opcode_Decoded *rd, int i, int v) put_reg (o->reg, get_reg (o->reg) - size2bytes[o->size]); /* fall through */ case RX_Operand_Postinc: /* [Rn+] */ + case RX_Operand_Zero_Indirect: /* [Rn + 0] */ case RX_Operand_Indirect: /* [Rn + addend] */ case RX_Operand_TwoReg: /* [Rn + scale * R2] */ @@ -597,6 +606,7 @@ put_op (const RX_Opcode_Decoded *rd, int i, int v) switch (o->size) { + default: case RX_AnySize: rx_abort (); @@ -1504,6 +1514,10 @@ decode_opcode () case RXO_nop: case RXO_nop2: case RXO_nop3: + case RXO_nop4: + case RXO_nop5: + case RXO_nop6: + case RXO_nop7: E1; break;