@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2022 Free Software Foundation, Inc.
+Copyright (C) 1996-2022 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2022 Free Software Foundation, Inc.
+Copyright (C) 1996-2022 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,13 +17,22 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
#ifndef CRIS_ARCH_H
#define CRIS_ARCH_H
+#define TARGET_BIG_ENDIAN 1
+
+#define WI SI
+#define UWI USI
+#define AI USI
+
+#define IAI USI
+
/* Enum declaration for model types. */
typedef enum model_type {
MODEL_CRISV10, MODEL_CRISV32, MODEL_MAX
@@ -36,10 +45,10 @@ typedef enum unit_type {
UNIT_NONE, UNIT_CRISV10_U_MOVEM, UNIT_CRISV10_U_MULTIPLY, UNIT_CRISV10_U_SKIP4
, UNIT_CRISV10_U_STALL, UNIT_CRISV10_U_CONST32, UNIT_CRISV10_U_CONST16, UNIT_CRISV10_U_MEM
, UNIT_CRISV10_U_EXEC, UNIT_CRISV32_U_EXEC_TO_SR, UNIT_CRISV32_U_EXEC_MOVEM, UNIT_CRISV32_U_EXEC
- , UNIT_CRISV32_U_SKIP4, UNIT_CRISV32_U_CONST32, UNIT_CRISV32_U_CONST16, UNIT_CRISV32_U_JUMP
- , UNIT_CRISV32_U_JUMP_SR, UNIT_CRISV32_U_JUMP_R, UNIT_CRISV32_U_BRANCH, UNIT_CRISV32_U_MULTIPLY
- , UNIT_CRISV32_U_MOVEM_MTOR, UNIT_CRISV32_U_MOVEM_RTOM, UNIT_CRISV32_U_MEM_W, UNIT_CRISV32_U_MEM_R
- , UNIT_CRISV32_U_MEM, UNIT_MAX
+ , UNIT_CRISV32_U_STALL, UNIT_CRISV32_U_SKIP4, UNIT_CRISV32_U_CONST32, UNIT_CRISV32_U_CONST16
+ , UNIT_CRISV32_U_JUMP, UNIT_CRISV32_U_JUMP_SR, UNIT_CRISV32_U_JUMP_R, UNIT_CRISV32_U_BRANCH
+ , UNIT_CRISV32_U_MULTIPLY, UNIT_CRISV32_U_MOVEM_MTOR, UNIT_CRISV32_U_MOVEM_RTOM, UNIT_CRISV32_U_MEM_W
+ , UNIT_CRISV32_U_MEM_R, UNIT_CRISV32_U_MEM, UNIT_MAX
} UNIT_TYPE;
#define MAX_UNITS (4)
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2022 Free Software Foundation, Inc.
+Copyright (C) 1996-2022 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2022 Free Software Foundation, Inc.
+Copyright (C) 1996-2022 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@@ -490,3 +491,4 @@ crisv10f_h_prefixreg_pre_v32_set (SIM_CPU *current_cpu, SI newval)
{
CPU (h_prefixreg_pre_v32) = newval;
}
+
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2022 Free Software Foundation, Inc.
+Copyright (C) 1996-2022 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2022 Free Software Foundation, Inc.
+Copyright (C) 1996-2022 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@@ -586,3 +587,4 @@ crisv32f_h_prefixreg_v32_set (SIM_CPU *current_cpu, SI newval)
{
SET_H_PREFIXREG_V32 (newval);
}
+
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2022 Free Software Foundation, Inc.
+Copyright (C) 1996-2022 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2022 Free Software Foundation, Inc.
+Copyright (C) 1996-2022 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@@ -41,12 +42,12 @@ static IDESC crisv10f_insn_data[CRISV10F_INSN__MAX];
static const struct insn_sem crisv10f_insn_sem[] =
{
- { VIRTUAL_INSN_X_INVALID, CRISV10F_INSN_X_INVALID, CRISV10F_SFMT_EMPTY },
- { VIRTUAL_INSN_X_AFTER, CRISV10F_INSN_X_AFTER, CRISV10F_SFMT_EMPTY },
- { VIRTUAL_INSN_X_BEFORE, CRISV10F_INSN_X_BEFORE, CRISV10F_SFMT_EMPTY },
- { VIRTUAL_INSN_X_CTI_CHAIN, CRISV10F_INSN_X_CTI_CHAIN, CRISV10F_SFMT_EMPTY },
- { VIRTUAL_INSN_X_CHAIN, CRISV10F_INSN_X_CHAIN, CRISV10F_SFMT_EMPTY },
- { VIRTUAL_INSN_X_BEGIN, CRISV10F_INSN_X_BEGIN, CRISV10F_SFMT_EMPTY },
+ { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_INVALID, CRISV10F_INSN_X_INVALID, CRISV10F_SFMT_EMPTY },
+ { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_AFTER, CRISV10F_INSN_X_AFTER, CRISV10F_SFMT_EMPTY },
+ { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_BEFORE, CRISV10F_INSN_X_BEFORE, CRISV10F_SFMT_EMPTY },
+ { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_CTI_CHAIN, CRISV10F_INSN_X_CTI_CHAIN, CRISV10F_SFMT_EMPTY },
+ { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_CHAIN, CRISV10F_INSN_X_CHAIN, CRISV10F_SFMT_EMPTY },
+ { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_BEGIN, CRISV10F_INSN_X_BEGIN, CRISV10F_SFMT_EMPTY },
{ CRIS_INSN_NOP, CRISV10F_INSN_NOP, CRISV10F_SFMT_NOP },
{ CRIS_INSN_MOVE_B_R, CRISV10F_INSN_MOVE_B_R, CRISV10F_SFMT_MOVE_B_R },
{ CRIS_INSN_MOVE_W_R, CRISV10F_INSN_MOVE_W_R, CRISV10F_SFMT_MOVE_B_R },
@@ -254,7 +255,7 @@ static const struct insn_sem crisv10f_insn_sem[] =
static const struct insn_sem crisv10f_insn_sem_invalid =
{
- VIRTUAL_INSN_X_INVALID, CRISV10F_INSN_X_INVALID, CRISV10F_SFMT_EMPTY
+ (CGEN_INSN_TYPE) VIRTUAL_INSN_X_INVALID, CRISV10F_INSN_X_INVALID, CRISV10F_SFMT_EMPTY
};
/* Initialize an IDESC from the compile-time computable parts. */
@@ -303,7 +304,7 @@ crisv10f_init_idesc_table (SIM_CPU *cpu)
init_idesc (cpu, id, t);
/* Now fill in the values for the chosen cpu. */
- for (t = crisv10f_insn_sem, tend = t + ARRAY_SIZE (crisv10f_insn_sem);
+ for (t = crisv10f_insn_sem, tend = t + sizeof (crisv10f_insn_sem) / sizeof (*t);
t != tend; ++t)
{
init_idesc (cpu, & table[t->index], t);
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2022 Free Software Foundation, Inc.
+Copyright (C) 1996-2022 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@@ -30,7 +31,6 @@ extern const IDESC *crisv10f_decode (SIM_CPU *, IADDR,
extern void crisv10f_init_idesc_table (SIM_CPU *);
extern void crisv10f_sem_init_idesc_table (SIM_CPU *);
extern void crisv10f_semf_init_idesc_table (SIM_CPU *);
-extern void crisv10f_specific_init (SIM_CPU *);
/* Enum declaration for instructions in cpu family crisv10f. */
typedef enum crisv10f_insn_type {
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2022 Free Software Foundation, Inc.
+Copyright (C) 1996-2022 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@@ -41,12 +42,12 @@ static IDESC crisv32f_insn_data[CRISV32F_INSN__MAX];
static const struct insn_sem crisv32f_insn_sem[] =
{
- { VIRTUAL_INSN_X_INVALID, CRISV32F_INSN_X_INVALID, CRISV32F_SFMT_EMPTY },
- { VIRTUAL_INSN_X_AFTER, CRISV32F_INSN_X_AFTER, CRISV32F_SFMT_EMPTY },
- { VIRTUAL_INSN_X_BEFORE, CRISV32F_INSN_X_BEFORE, CRISV32F_SFMT_EMPTY },
- { VIRTUAL_INSN_X_CTI_CHAIN, CRISV32F_INSN_X_CTI_CHAIN, CRISV32F_SFMT_EMPTY },
- { VIRTUAL_INSN_X_CHAIN, CRISV32F_INSN_X_CHAIN, CRISV32F_SFMT_EMPTY },
- { VIRTUAL_INSN_X_BEGIN, CRISV32F_INSN_X_BEGIN, CRISV32F_SFMT_EMPTY },
+ { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_INVALID, CRISV32F_INSN_X_INVALID, CRISV32F_SFMT_EMPTY },
+ { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_AFTER, CRISV32F_INSN_X_AFTER, CRISV32F_SFMT_EMPTY },
+ { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_BEFORE, CRISV32F_INSN_X_BEFORE, CRISV32F_SFMT_EMPTY },
+ { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_CTI_CHAIN, CRISV32F_INSN_X_CTI_CHAIN, CRISV32F_SFMT_EMPTY },
+ { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_CHAIN, CRISV32F_INSN_X_CHAIN, CRISV32F_SFMT_EMPTY },
+ { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_BEGIN, CRISV32F_INSN_X_BEGIN, CRISV32F_SFMT_EMPTY },
{ CRIS_INSN_MOVE_B_R, CRISV32F_INSN_MOVE_B_R, CRISV32F_SFMT_MOVE_B_R },
{ CRIS_INSN_MOVE_W_R, CRISV32F_INSN_MOVE_W_R, CRISV32F_SFMT_MOVE_B_R },
{ CRIS_INSN_MOVE_D_R, CRISV32F_INSN_MOVE_D_R, CRISV32F_SFMT_MOVE_D_R },
@@ -258,7 +259,7 @@ static const struct insn_sem crisv32f_insn_sem[] =
static const struct insn_sem crisv32f_insn_sem_invalid =
{
- VIRTUAL_INSN_X_INVALID, CRISV32F_INSN_X_INVALID, CRISV32F_SFMT_EMPTY
+ (CGEN_INSN_TYPE) VIRTUAL_INSN_X_INVALID, CRISV32F_INSN_X_INVALID, CRISV32F_SFMT_EMPTY
};
/* Initialize an IDESC from the compile-time computable parts. */
@@ -307,7 +308,7 @@ crisv32f_init_idesc_table (SIM_CPU *cpu)
init_idesc (cpu, id, t);
/* Now fill in the values for the chosen cpu. */
- for (t = crisv32f_insn_sem, tend = t + ARRAY_SIZE (crisv32f_insn_sem);
+ for (t = crisv32f_insn_sem, tend = t + sizeof (crisv32f_insn_sem) / sizeof (*t);
t != tend; ++t)
{
init_idesc (cpu, & table[t->index], t);
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2022 Free Software Foundation, Inc.
+Copyright (C) 1996-2022 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@@ -30,7 +31,6 @@ extern const IDESC *crisv32f_decode (SIM_CPU *, IADDR,
extern void crisv32f_init_idesc_table (SIM_CPU *);
extern void crisv32f_sem_init_idesc_table (SIM_CPU *);
extern void crisv32f_semf_init_idesc_table (SIM_CPU *);
-extern void crisv32f_specific_init (SIM_CPU *);
/* Enum declaration for instructions in cpu family crisv32f. */
typedef enum crisv32f_insn_type {
@@ -126,8 +126,8 @@ typedef enum crisv32f_sfmt_type {
extern int crisv32f_model_crisv32_u_exec_to_sr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rs*/, INT /*Pd*/);
extern int crisv32f_model_crisv32_u_exec_movem (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rs*/, INT /*Rd*/);
extern int crisv32f_model_crisv32_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rd*/, INT /*Rs*/, INT /*Rd*/);
-extern int crisv32f_model_crisv32_u_skip4 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int crisv32f_model_crisv32_u_stall (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+extern int crisv32f_model_crisv32_u_skip4 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int crisv32f_model_crisv32_u_const32 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int crisv32f_model_crisv32_u_const16 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int crisv32f_model_crisv32_u_jump (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Pd*/);
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2022 Free Software Foundation, Inc.
+Copyright (C) 1996-2022 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2022 Free Software Foundation, Inc.
+Copyright (C) 1996-2022 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2022 Free Software Foundation, Inc.
+Copyright (C) 1996-2022 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@@ -260,7 +261,7 @@ This file is part of the GNU simulators.
/* If hyper-fast [well not unnecessarily slow] execution is selected, turn
off frills like tracing and profiling. */
-/* FIXME: A better way would be to have CGEN_TRACE_RESULT check for something
+/* FIXME: A better way would be to have TRACE_RESULT check for something
that can cause it to be optimized out. Another way would be to emit
special handlers into the instruction "stream". */
@@ -3379,6 +3380,7 @@ cgen_rtx_error (current_cpu, "move-spr-r from unimplemented register");
SI tmp_rno;
SI tmp_newval;
tmp_rno = FLD (f_operand2);
+ tmp_newval = 0;
if (EQSI (tmp_rno, 5)) {
tmp_newval = EXTHISI (({ SI tmp_addr;
HI tmp_tmp_mem;
@@ -10993,7 +10995,8 @@ SET_H_VBIT_MOVE (0);
tmp_tmpd = ({ SI tmp_tmpcode;
SI tmp_tmpval;
SI tmp_tmpres;
- tmp_tmpcode = FLD (f_operand2);
+ tmp_tmpres = 0;
+; tmp_tmpcode = FLD (f_operand2);
; tmp_tmpval = tmp_tmps;
; if (EQSI (tmp_tmpcode, 0)) {
tmp_tmpres = (cgen_rtx_error (current_cpu, "SWAP without swap modifier isn't implemented"), 0);
@@ -12060,7 +12063,8 @@ if (NESI (ANDSI (tmp_tmp, SLLSI (1, 7)), 0)) {
BI tmp_truthval;
tmp_truthval = ({ SI tmp_tmpcond;
BI tmp_condres;
- tmp_tmpcond = FLD (f_operand2);
+ tmp_condres = 0;
+; tmp_tmpcond = FLD (f_operand2);
; if (EQSI (tmp_tmpcond, 0)) {
tmp_condres = NOTBI (CPU (h_cbit));
}
@@ -12192,7 +12196,8 @@ if (tmp_truthval) {
BI tmp_truthval;
tmp_truthval = ({ SI tmp_tmpcond;
BI tmp_condres;
- tmp_tmpcond = FLD (f_operand2);
+ tmp_condres = 0;
+; tmp_tmpcond = FLD (f_operand2);
; if (EQSI (tmp_tmpcond, 0)) {
tmp_condres = NOTBI (CPU (h_cbit));
}
@@ -13065,7 +13070,8 @@ SET_H_VBIT_MOVE (0);
BI tmp_truthval;
tmp_truthval = ({ SI tmp_tmpcond;
BI tmp_condres;
- tmp_tmpcond = FLD (f_operand2);
+ tmp_condres = 0;
+; tmp_tmpcond = FLD (f_operand2);
; if (EQSI (tmp_tmpcond, 0)) {
tmp_condres = NOTBI (CPU (h_cbit));
}
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2022 Free Software Foundation, Inc.
+Copyright (C) 1996-2022 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, see <http://www.gnu.org/licenses/>.
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@@ -264,7 +265,7 @@ This file is part of the GNU simulators.
/* If hyper-fast [well not unnecessarily slow] execution is selected, turn
off frills like tracing and profiling. */
-/* FIXME: A better way would be to have CGEN_TRACE_RESULT check for something
+/* FIXME: A better way would be to have TRACE_RESULT check for something
that can cause it to be optimized out. Another way would be to emit
special handlers into the instruction "stream". */
@@ -3291,6 +3292,7 @@ cgen_rtx_error (current_cpu, "move-spr-r from unimplemented register");
SI tmp_rno;
SI tmp_newval;
tmp_rno = FLD (f_operand2);
+ tmp_newval = 0;
if (EQSI (tmp_rno, 2)) {
tmp_newval = ({ SI tmp_addr;
SI tmp_tmp_mem;
@@ -11263,7 +11265,8 @@ SET_H_VBIT_MOVE (0);
tmp_tmpd = ({ SI tmp_tmpcode;
SI tmp_tmpval;
SI tmp_tmpres;
- tmp_tmpcode = FLD (f_operand2);
+ tmp_tmpres = 0;
+; tmp_tmpcode = FLD (f_operand2);
; tmp_tmpval = tmp_tmps;
; if (EQSI (tmp_tmpcode, 0)) {
tmp_tmpres = (cgen_rtx_error (current_cpu, "SWAP without swap modifier isn't implemented"), 0);
@@ -12460,7 +12463,8 @@ crisv32f_rfg_handler (current_cpu, pc);
BI tmp_truthval;
tmp_truthval = ({ SI tmp_tmpcond;
BI tmp_condres;
- tmp_tmpcond = FLD (f_operand2);
+ tmp_condres = 0;
+; tmp_tmpcond = FLD (f_operand2);
; if (EQSI (tmp_tmpcond, 0)) {
tmp_condres = NOTBI (CPU (h_cbit));
}
@@ -12592,7 +12596,8 @@ if (tmp_truthval) {
BI tmp_truthval;
tmp_truthval = ({ SI tmp_tmpcond;
BI tmp_condres;
- tmp_tmpcond = FLD (f_operand2);
+ tmp_condres = 0;
+; tmp_tmpcond = FLD (f_operand2);
; if (EQSI (tmp_tmpcond, 0)) {
tmp_condres = NOTBI (CPU (h_cbit));
}
@@ -13380,7 +13385,8 @@ SET_H_VBIT_MOVE (0);
BI tmp_truthval;
tmp_truthval = ({ SI tmp_tmpcond;
BI tmp_condres;
- tmp_tmpcond = FLD (f_operand2);
+ tmp_condres = 0;
+; tmp_tmpcond = FLD (f_operand2);
; if (EQSI (tmp_tmpcond, 0)) {
tmp_condres = NOTBI (CPU (h_cbit));
}