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SRVR:AM3PR08MB0104; BCL:0; PCL:0; RULEID:; SRVR:AM3PR08MB0104; x-forefront-prvs: 0289B6431E x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(6009001)(39860400002)(39400400002)(39840400002)(39450400003)(39850400002)(39410400002)(377424004)(24454002)(66066001)(82746002)(7736002)(305945005)(93886004)(1411001)(36756003)(5250100002)(189998001)(229853002)(83716003)(54356999)(76176999)(50986999)(5660300001)(25786009)(6512007)(54906002)(81166006)(6436002)(53546009)(6486002)(2906002)(99286003)(3846002)(6116002)(8676002)(102836003)(86362001)(6506006)(53936002)(39060400002)(38730400002)(2950100002)(3660700001)(8936002)(3280700002)(110136004)(4326008)(6916009)(33656002)(2900100001)(6246003); DIR:OUT; SFP:1101; SCL:1; SRVR:AM3PR08MB0104; H:AM3PR08MB0101.eurprd08.prod.outlook.com; FPR:; SPF:None; MLV:ovrnspm; PTR:InfoNoRecords; LANG:en; spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-ID: <1E5D99A16D2B0E41AF348F0E588D1CAF@eurprd08.prod.outlook.com> MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-originalarrivaltime: 26 Apr 2017 09:59:54.9234 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM3PR08MB0104 > On 25 Apr 2017, at 16:39, Yao Qi wrote: > > Alan Hayward writes: > >> @@ -559,16 +562,15 @@ xtensa_pseudo_register_read (struct gdbarch *gdbarch, >> && (regnum >= gdbarch_tdep (gdbarch)->a0_base) >> && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)) >> { >> - gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE); >> + ULONGEST value; >> enum register_status status; >> >> - status = regcache_raw_read (regcache, >> - gdbarch_tdep (gdbarch)->wb_regnum, >> - buf); >> + status = regcache_raw_read_unsigned (regcache, >> + gdbarch_tdep (gdbarch)->wb_regnum, >> + &value); >> if (status != REG_VALID) >> return status; >> - regnum = arreg_number (gdbarch, regnum, >> - extract_unsigned_integer (buf, 4, byte_order)); >> + regnum = arreg_number (gdbarch, regnum, value); >> } >> >> /* We can always read non-pseudo registers. */ >> @@ -656,12 +658,10 @@ xtensa_pseudo_register_write (struct gdbarch *gdbarch, >> && (regnum >= gdbarch_tdep (gdbarch)->a0_base) >> && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)) >> { >> - gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE); >> - >> - regcache_raw_read (regcache, >> - gdbarch_tdep (gdbarch)->wb_regnum, buf); >> - regnum = arreg_number (gdbarch, regnum, >> - extract_unsigned_integer (buf, 4, byte_order)); >> + ULONGEST value; >> + regcache_raw_read_unsigned (regcache, >> + gdbarch_tdep (gdbarch)->wb_regnum, &value); >> + regnum = arreg_number (gdbarch, regnum, value); > > This part of patch is OK, but the part using XTENSA_MAX_REGISTER_SIZE > still needs some review. > > -- > Yao (齐尧) Ok, Above committed with: 2017-04-26 Alan Hayward * xtensa-tdep.c (xtensa_pseudo_register_read): Use regcache_raw_read_unsigned. (xtensa_pseudo_register_write): Likewise. This leaves the following left to review (below). Looking at the code, I'm still a little unsure exactly how "value" is being used. "value" is declared as max register size, rounded up to the next int. Looking at the use of value, I think the code requires max size of a register multiplied by the value in reg->mask + 1 - and checking xtensa-config.c, this never goes above one. The comment also states the size of a masked register is never greater than 32bits. Maybe the value should be given a size of 32bits * (mask->count + 1) ? 2017-04-06 Alan Hayward * xtensa-tdep.c (XTENSA_MAX_REGISTER_SIZE): Add. (xtensa_register_write_masked): Use XTENSA_MAX_REGISTER_SIZE. (xtensa_register_read_masked): Likewise. diff --git a/gdb/xtensa-tdep.c b/gdb/xtensa-tdep.c index 0a4ed37cf9582a7aa43ec601fc013f1f93624a39..e79c925b345a8bd03e3a674c731c00e86f1ea39a 100644 --- a/gdb/xtensa-tdep.c +++ b/gdb/xtensa-tdep.c @@ -120,6 +120,9 @@ static unsigned int xtensa_debug_level = 0; #define PS_WOE (1<<18) #define PS_EXC (1<<4) +/* Big enough to hold the size of the largest register in bytes. */ +#define XTENSA_MAX_REGISTER_SIZE 16 + static int windowing_enabled (struct gdbarch *gdbarch, unsigned int ps) { @@ -370,7 +373,7 @@ static void xtensa_register_write_masked (struct regcache *regcache, xtensa_register_t *reg, const gdb_byte *buffer) { - unsigned int value[(MAX_REGISTER_SIZE + 3) / 4]; + unsigned int value[(XTENSA_MAX_REGISTER_SIZE + 3) / 4]; const xtensa_mask_t *mask = reg->mask; int shift = 0; /* Shift for next mask (mod 32). */ @@ -454,7 +457,7 @@ static enum register_status xtensa_register_read_masked (struct regcache *regcache, xtensa_register_t *reg, gdb_byte *buffer) { - unsigned int value[(MAX_REGISTER_SIZE + 3) / 4]; + unsigned int value[(XTENSA_MAX_REGISTER_SIZE + 3) / 4]; const xtensa_mask_t *mask = reg->mask; int shift = 0;