From patchwork Thu Nov 29 16:48:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Burgess X-Patchwork-Id: 30392 Received: (qmail 33992 invoked by alias); 29 Nov 2018 16:50:05 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 27937 invoked by uid 89); 29 Nov 2018 16:48:32 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=Hx-spam-relays-external:209.85.128.68, H*RU:209.85.128.68, our X-HELO: mail-wm1-f68.google.com Received: from mail-wm1-f68.google.com (HELO mail-wm1-f68.google.com) (209.85.128.68) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 29 Nov 2018 16:48:30 +0000 Received: by mail-wm1-f68.google.com with SMTP id s14so2998587wmh.1 for ; Thu, 29 Nov 2018 08:48:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=jNLMc9kvbnfbL0/gJDis1KPoRW0sY/FwzL7g6dvvfGU=; b=aUzs0eybAvlZ7SkGZrFcpnYQzESD/aDVj5/ALasHjaiUDXMDuhGRRDSLoy5R2Y9Ok6 rMOlEEBtRYkgFYm8wZJdu6QQ8aAnV3r2dFOtHdFt9CrP+HuYY4Fjwd65rSlwj7B9j3TZ 11o/zozbv6SAGVqkgzQBmuoBbCk/ZHQ10y6JRYixmCFna8oYTWkxKV/daDefiKslqgOF HZdDlsSWQqmPfzUUwapI+RW7I482f35CV5YOpaaMtm9EwHTDzlw5Hx/dJHPr1TwyaGdA XRrXK7z4o6NEnJjXOMR1+OoXvqyJpfZN71Wo/MSJtE8RvJ+4Edt+SJj/7IfJa7aXRxlJ vdIg== Return-Path: Received: from localhost (host86-156-236-171.range86-156.btcentralplus.com. [86.156.236.171]) by smtp.gmail.com with ESMTPSA id z12sm3193090wrh.35.2018.11.29.08.48.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 29 Nov 2018 08:48:23 -0800 (PST) From: Andrew Burgess To: gdb-patches@sourceware.org Cc: jimw@sifive.com, palmer@sifive.com, jhb@FreeBSD.org, Andrew Burgess Subject: [PATCH 4/4] gdb/riscv: Add read_description method for riscv_linux_nat_target Date: Thu, 29 Nov 2018 16:48:13 +0000 Message-Id: <39fcb759028c9fe3b17c8fdd2469a7238f231296.1543509416.git.andrew.burgess@embecosm.com> In-Reply-To: References: In-Reply-To: References: X-IsSubscribed: yes Adds riscv_linux_nat_target::read_description method to find a suitable target description for the native linux target we are running on. Currently this will supply a suitably sized set of x-registers, and will probe the kernel to see if the f-registers are readable. If they are readable then we currently assume that the f-registers are the same size as the x-registers as I don't know of a good way to probe the f-register length. This will obviously need fixing in future. As of Linux 4.19 there is no ptrace support for reading the f-registers, this should appear in 4.20, so right now we only return target descriptions without f-registers. gdb/ChangeLog: * riscv-linux-nat.c: Add 'inferior.h' and 'target-descriptions.h' header files. (riscv_linux_nat_target::read_description): New method. --- gdb/ChangeLog | 6 ++++++ gdb/riscv-linux-nat.c | 38 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/gdb/riscv-linux-nat.c b/gdb/riscv-linux-nat.c index d51f6e30218..f0705bc763f 100644 --- a/gdb/riscv-linux-nat.c +++ b/gdb/riscv-linux-nat.c @@ -21,6 +21,8 @@ #include "gregset.h" #include "linux-nat.h" #include "riscv-tdep.h" +#include "inferior.h" +#include "target-descriptions.h" #include "elf/common.h" @@ -34,6 +36,9 @@ public: /* Add our register access methods. */ void fetch_registers (struct regcache *regcache, int regnum) override; void store_registers (struct regcache *regcache, int regnum) override; + + /* Read suitable target description. */ + const struct target_desc *read_description () override; }; static riscv_linux_nat_target the_riscv_linux_nat_target; @@ -155,6 +160,39 @@ fill_fpregset (const struct regcache *regcache, prfpregset_t *fpregs, regcache->raw_collect (RISCV_CSR_FCSR_REGNUM, &fpregs->__d.__fcsr); } +/* Return a target description for the current target. */ + +const struct target_desc * +riscv_linux_nat_target::read_description () +{ + struct riscv_gdbarch_features features; + struct iovec iov; + elf_fpregset_t regs; + int tid; + + /* Figuring out xlen is easy. */ + features.xlen = sizeof (elf_greg_t); + + tid = inferior_ptid.lwp (); + + iov.iov_base = ®s; + iov.iov_len = sizeof (regs); + + /* Can we fetch the f-registers? */ + if (ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, + (PTRACE_TYPE_ARG3) &iov) == -1) + features.flen = 0; /* No f-registers. */ + else + { + /* TODO: We need a way to figure out the actual length of the + f-registers. We could have 64-bit x-registers, with 32-bit + f-registers. For now, just assumed xlen and flen match. */ + features.flen = features.xlen; + } + + return riscv_create_target_description (features); +} + /* Fetch REGNUM (or all registers if REGNUM == -1) from the target into REGCACHE using PTRACE_GETREGSET. */