From patchwork Thu Jun 8 09:42:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alan Hayward X-Patchwork-Id: 20846 Received: (qmail 112684 invoked by alias); 8 Jun 2017 09:42:15 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 111569 invoked by uid 89); 8 Jun 2017 09:42:14 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.9 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, MIME_BASE64_BLANKS, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: EUR01-VE1-obe.outbound.protection.outlook.com Received: from mail-ve1eur01on0057.outbound.protection.outlook.com (HELO EUR01-VE1-obe.outbound.protection.outlook.com) (104.47.1.57) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 08 Jun 2017 09:42:13 +0000 Received: from AM3PR08MB0101.eurprd08.prod.outlook.com (10.160.211.19) by AM3PR08MB0103.eurprd08.prod.outlook.com (10.160.211.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1157.12; Thu, 8 Jun 2017 09:42:14 +0000 Received: from AM3PR08MB0101.eurprd08.prod.outlook.com ([fe80::f0a8:fd0f:69e1:e280]) by AM3PR08MB0101.eurprd08.prod.outlook.com ([fe80::f0a8:fd0f:69e1:e280%17]) with mapi id 15.01.1157.012; Thu, 8 Jun 2017 09:42:14 +0000 From: Alan Hayward To: Yao Qi , "gdb-patches@sourceware.org" CC: nd Subject: Re: [PATCH 10/11] Add XTENSA_MAX_REGISTER_SIZE Date: Thu, 8 Jun 2017 09:42:14 +0000 Message-ID: <3966B257-0F47-49C3-A1C1-F901D8E731AC@arm.com> References: <86y3vfp308.fsf@gmail.com> <868tmosdi0.fsf@gmail.com> <49176F63-F5C5-43C2-A21D-A7642F4ACB80@arm.com> In-Reply-To: <49176F63-F5C5-43C2-A21D-A7642F4ACB80@arm.com> authentication-results: gmail.com; dkim=none (message not signed) header.d=none; gmail.com; dmarc=none action=none header.from=arm.com; x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM3PR08MB0103; 7:EFUXeJMABQown+Xwadu7klYtOWkbvgISCbGMh5DZJzDJsTm3xpLe07UOwnxADPiimALgBVikJlDSdzyBV/+iDgueE7vFwt81biBpVeG9l1AAeiWkGk+QCI9cHkYdXPLNn82aOjU5Cj1HG+wCyjm50YKHa0f5+9S74Oo0eQZxdNujdZ0kO4MVHjIqSr52jcnaisczlcO3MdmsIA2fhRZuRXCFHs3k6ep6YXsfTrtOryBD5MjmvQIB8rK51nG8csHtAgxa4fdbfRnmnd9jiePv0GBH8h9KDbEYOJHaWHpfqDuvksF+sJv+GBMN4Dy0uJHHdVB9fFw0BzgF2/+Cbf+T8w== x-ms-traffictypediagnostic: AM3PR08MB0103: x-ms-office365-filtering-correlation-id: 164f1ed1-a03d-4121-691a-08d4ae52a52a x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001)(2017030254075)(48565401081)(201703131423075)(201703031133081)(201702281549075); SRVR:AM3PR08MB0103; nodisclaimer: True x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(180628864354917); x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6040450)(601004)(2401047)(8121501046)(5005006)(10201501046)(3002001)(100000703101)(100105400095)(93006095)(93001095)(6055026)(6041248)(20161123562025)(20161123560025)(20161123564025)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123555025)(20161123558100)(6072148)(100000704101)(100105200095)(100000705101)(100105500095); SRVR:AM3PR08MB0103; BCL:0; PCL:0; RULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095); SRVR:AM3PR08MB0103; x-forefront-prvs: 0332AACBC3 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(6009001)(39850400002)(39400400002)(39840400002)(39410400002)(39450400003)(377424004)(24454002)(53546009)(6246003)(229853002)(6436002)(6506006)(36756003)(8936002)(25786009)(6486002)(81166006)(93886004)(5660300001)(189998001)(5250100002)(14454004)(2501003)(8676002)(66066001)(478600001)(39060400002)(38730400002)(72206003)(305945005)(4326008)(7736002)(76176999)(50986999)(3280700002)(2900100001)(3660700001)(33656002)(99286003)(3846002)(86362001)(83716003)(2906002)(53936002)(102836003)(6116002)(82746002)(6512007)(2950100002)(54356999); DIR:OUT; SFP:1101; SCL:1; SRVR:AM3PR08MB0103; H:AM3PR08MB0101.eurprd08.prod.outlook.com; FPR:; SPF:None; MLV:ovrnspm; PTR:InfoNoRecords; LANG:en; spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-ID: MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Jun 2017 09:42:14.6422 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM3PR08MB0103 > On 26 Apr 2017, at 10:59, Alan Hayward wrote: > > >> On 25 Apr 2017, at 16:39, Yao Qi wrote: >> >> Alan Hayward writes: >> I’ve rebased this patch due to Yao’s unit test changes. XTENSA_MAX_REGISTER_SIZE is set to 64 to ensure nothing breaks. I don't have a XTENSA machine to test on. Tested on a --enable-targets=all and asan build using make check with board files unix, native-gdbserver and unittest Ok to commit? Alan. 2017-06-08 Alan Hayward * xtensa-tdep.c (XTENSA_MAX_REGISTER_SIZE): Add. (xtensa_register_write_masked): Use XTENSA_MAX_REGISTER_SIZE. (xtensa_register_read_masked): Likewise. diff --git a/gdb/xtensa-tdep.c b/gdb/xtensa-tdep.c index f9e858473a409ff082d30f9ff474d48da63903e3..f875f20d32b68abc37e3db37ab3e6053918536e5 100644 --- a/gdb/xtensa-tdep.c +++ b/gdb/xtensa-tdep.c @@ -120,6 +120,9 @@ static unsigned int xtensa_debug_level = 0; #define PS_WOE (1<<18) #define PS_EXC (1<<4) +/* Big enough to hold the size of the largest register in bytes. */ +#define XTENSA_MAX_REGISTER_SIZE 64 + static int windowing_enabled (struct gdbarch *gdbarch, unsigned int ps) { @@ -370,7 +373,7 @@ static void xtensa_register_write_masked (struct regcache *regcache, xtensa_register_t *reg, const gdb_byte *buffer) { - unsigned int value[(MAX_REGISTER_SIZE + 3) / 4]; + unsigned int value[(XTENSA_MAX_REGISTER_SIZE + 3) / 4]; const xtensa_mask_t *mask = reg->mask; int shift = 0; /* Shift for next mask (mod 32). */ @@ -454,7 +457,7 @@ static enum register_status xtensa_register_read_masked (struct regcache *regcache, xtensa_register_t *reg, gdb_byte *buffer) { - unsigned int value[(MAX_REGISTER_SIZE + 3) / 4]; + unsigned int value[(XTENSA_MAX_REGISTER_SIZE + 3) / 4]; const xtensa_mask_t *mask = reg->mask; int shift = 0;