From patchwork Thu Dec 13 20:57:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Burgess X-Patchwork-Id: 30666 Received: (qmail 38794 invoked by alias); 13 Dec 2018 20:58:03 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 38683 invoked by uid 89); 13 Dec 2018 20:58:02 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=sk:riscv_c X-HELO: mail-wr1-f65.google.com Received: from mail-wr1-f65.google.com (HELO mail-wr1-f65.google.com) (209.85.221.65) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 13 Dec 2018 20:58:00 +0000 Received: by mail-wr1-f65.google.com with SMTP id p4so3391218wrt.7 for ; Thu, 13 Dec 2018 12:58:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=LjVyG2kckXGX4hjnGL+ydLVk4vr+2ULRvp6zlPWjGBs=; b=Kikl8wbo7K8O+yP8XLQKEJzCyQojqjHKS/WFPyLXhkrWiPkuTzD/igd46bwTlwSg/a u3s6DoeTbMCOOd+O/qMOD2oD2HNLzAd7EmuzI7d29C7mfh7R/+vYRLoMvpjxppz4ZUnk cy7TKjvQBaCQWm4AX/jpYGAWnUFvLovufI5OTZtVY1jpqn7eo+yuA0KkoAPMLAA8XNv6 t7uGDfboAshhFk8SH5ltqgJacipvYijdLdX7sdC0BacFIFCaHyebM2Qyveb4lvIsMXFR e61clQWELV5h62jvYxoYi3NPU5LuADheIx+J2z2tAeumSFVVewmTcpKPueAUnjoD8Fr/ 4acQ== Return-Path: Received: from localhost ([176.12.107.132]) by smtp.gmail.com with ESMTPSA id j8sm5004866wmd.0.2018.12.13.12.57.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 13 Dec 2018 12:57:57 -0800 (PST) From: Andrew Burgess To: gdb-patches@sourceware.org Cc: jimw@sifive.com, palmer@sifive.com, jhb@FreeBSD.org, Andrew Burgess Subject: [PATCH 2/2] gdb/riscv: Add float status registers to save and restore reggroups Date: Thu, 13 Dec 2018 20:57:50 +0000 Message-Id: <23ff86fa4276a041225e325eb863280fe2175b76.1544734579.git.andrew.burgess@embecosm.com> In-Reply-To: References: In-Reply-To: References: X-IsSubscribed: yes We should save and restore the floating point status registers. This became an issue when testing 32-bit float on a target with 64-bit with the gdb.base/callfuncs.exp test. gdb/ChangeLog: * riscv-tdep.c (riscv_register_reggroup_p): Save and restore fcsr, fflags, and frm registers. --- gdb/ChangeLog | 5 +++++ gdb/riscv-tdep.c | 5 ++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index 3b737064612..8b542a11b77 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -896,7 +896,10 @@ riscv_register_reggroup_p (struct gdbarch *gdbarch, int regnum, else if (reggroup == restore_reggroup || reggroup == save_reggroup) { if (riscv_has_fp_regs (gdbarch)) - return regnum <= RISCV_LAST_FP_REGNUM; + return (regnum <= RISCV_LAST_FP_REGNUM + || regnum == RISCV_CSR_FCSR_REGNUM + || regnum == RISCV_CSR_FFLAGS_REGNUM + || regnum == RISCV_CSR_FRM_REGNUM); else return regnum < RISCV_FIRST_FP_REGNUM; }