[3/3] gdb/sim/riscv: Fix c-ext.s test on big-endian

Message ID 20251216125949.560864-4-aleksa.paunovic@htecgroup.com
State New
Headers
Series gdb/sim/riscv: Various big-endian fixes. |

Commit Message

Aleksa Paunovic Dec. 16, 2025, 1:01 p.m. UTC
  Adds two new targets for the RISC-V testsuite. These targets are only
used for the C extension test currently, as this was the only place
within the testsuite where linker flags were explicitly passed.

Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
---
 sim/testsuite/riscv/allinsn.exp |  2 +-
 sim/testsuite/riscv/c-ext.s     | 16 +++++++++++-----
 2 files changed, 12 insertions(+), 6 deletions(-)
  

Patch

diff --git a/sim/testsuite/riscv/allinsn.exp b/sim/testsuite/riscv/allinsn.exp
index 9d4540394..d86ca3757 100644
--- a/sim/testsuite/riscv/allinsn.exp
+++ b/sim/testsuite/riscv/allinsn.exp
@@ -3,7 +3,7 @@ 
 sim_init
 
 # all machines
-set all_machs "riscv32 riscv64"
+set all_machs "riscv32 riscv64 riscv32be riscv64be"
 
 foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] {
     # If we're only testing specific files and this isn't one of them, skip it.
diff --git a/sim/testsuite/riscv/c-ext.s b/sim/testsuite/riscv/c-ext.s
index ad6e7b239..bae2c4d86 100644
--- a/sim/testsuite/riscv/c-ext.s
+++ b/sim/testsuite/riscv/c-ext.s
@@ -1,11 +1,17 @@ 
 # Basic Tests for C extension.
-# mach: riscv32 riscv64
-# sim(riscv32): --model RV32IC
-# sim(riscv64): --model RV64IC
+# mach: riscv32 riscv64 riscv32be riscv64be
+# sim(riscv32): --model RV32IC -EL
+# sim(riscv64): --model RV64IC -EL
+# sim(riscv32be): --model RV32IC -EB
+# sim(riscv64be): --model RV64IC -EB
 # ld(riscv32): -m elf32lriscv
 # ld(riscv64): -m elf64lriscv
-# as(riscv32): -march=rv32ic
-# as(riscv64): -march=rv64ic
+# ld(riscv32be): -m elf32briscv
+# ld(riscv64be): -m elf64briscv
+# as(riscv32): -march=rv32ic -mlittle-endian
+# as(riscv64): -march=rv64ic -mlittle-endian
+# as(riscv32be): -march=rv32ic -mbig-endian
+# as(riscv64be): -march=rv64ic -mbig-endian
 
 .include "testutils.inc"