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[2/3] gdb/sim/riscv: Fix default endianness

Message ID 20251216125949.560864-3-aleksa.paunovic@htecgroup.com
State New
Headers
Series gdb/sim/riscv: Various big-endian fixes. |

Commit Message

Aleksa Paunovic Dec. 16, 2025, 1:01 p.m. UTC 
  The default byte order for RISC-V was assumed to be little-endian,
which required passing -EB when running for big-endian targets.
This makes it easier to use the existing testing infrastructure
on big-endian builds.

Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
---
 sim/riscv/interp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/sim/riscv/interp.c b/sim/riscv/interp.c
index c94cf9c3e..a1ebcb78a 100644
--- a/sim/riscv/interp.c
+++ b/sim/riscv/interp.c
@@ -73,7 +73,7 @@  sim_open (SIM_OPEN_KIND kind, host_callback *callback,
   /* Set default options before parsing user options.  */
   STATE_MACHS (sd) = riscv_sim_machs;
   STATE_MODEL_NAME (sd) = WITH_TARGET_WORD_BITSIZE == 32 ? "RV32G" : "RV64G";
-  current_target_byte_order = BFD_ENDIAN_LITTLE;
+  current_target_byte_order = WITH_TARGET_BYTE_ORDER;
   callback->syscall_map = cb_riscv_syscall_map;
 
   /* The cpu data is kept in a separately allocated chunk of memory.  */