diff mbox series

[1/3] gdb/sim/riscv: Fix big-endian instruction fetch

Message ID 20251216125949.560864-2-aleksa.paunovic@htecgroup.com
State New
Headers
Series gdb/sim/riscv: Various big-endian fixes. |

Commit Message

Aleksa Paunovic Dec. 16, 2025, 1:01 p.m. UTC 
  RISC-V instructions are always stored in little-endian format.
The simplest way to handle this on big-endian platforms
is by swapping the bytes as we read instruction opcodes from memory.

Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
---
 sim/riscv/sim-main.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 172c593f7..a4f47c059 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -1341,6 +1341,8 @@  void step_once (SIM_CPU *cpu)
 		  NULL, 0, " "); /* Use a space for gcc warnings.  */
 
   iw = sim_core_read_aligned_2 (cpu, pc, exec_map, pc);
+  if (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+    iw = swap_2 (iw);
 
   len = riscv_insn_length (iw);
   if (len != 4 && len != 2)
@@ -1351,8 +1353,12 @@  void step_once (SIM_CPU *cpu)
     }
 
   if (len == 4)
-    iw |= ((unsigned_word) sim_core_read_aligned_2
-	   (cpu, pc, exec_map, pc + 2) << 16);
+    {
+      unsigned_word val = sim_core_read_aligned_2 (cpu, pc, exec_map, pc + 2);
+      if (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+	val = swap_2 (val);
+      iw |= (val << 16);
+    }
 
   TRACE_CORE (cpu, "0x%08" PRIxTW, iw);