From patchwork Fri May 24 09:55:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hui Li X-Patchwork-Id: 90800 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 102093858C66 for ; Fri, 24 May 2024 09:56:24 +0000 (GMT) X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 2E8D83858C41 for ; Fri, 24 May 2024 09:55:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2E8D83858C41 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 2E8D83858C41 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1716544521; cv=none; b=MByCP86t2GuwbsbOeNX+YTkD6jIBE0xm2ijNzHAUEh3GZuzH4hznvf1fS4gNyCL3j33YGocT/7YwUKtod+t8DAk17lh/MiXwc5lShwLcwVAEbSJN7qO3n5aFPZUsiIIKCocHfX39PQP32gujgRAJ2qKUnygJ0oz/tIJAbH4C2sE= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1716544521; c=relaxed/simple; bh=qaHI8jLohqjDijCN0259OBwOZrlw8VHdO4UkldCmFIU=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=t8SQd3/zjnzRTtkcjihAFjOOqvRcGvIl/QFVDhOCIF+F+8ndtN9n2LgFNOSOapQNXzDMnAoe6P9hXB//gPs0ZkSEDJjTYDjYUMRuYFzvBHu0YN31AKZ+U8FA7MW0T25ilKDRlhEWeqLhIpngtKHgMh+SBtmz7RGmWaMUnHCOmxo= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from loongson.cn (unknown [113.200.148.30]) by gateway (Coremail) with SMTP id _____8Dx9+kDZFBmBFYDAA--.3368S3; Fri, 24 May 2024 17:55:15 +0800 (CST) Received: from localhost.localdomain (unknown [113.200.148.30]) by localhost.localdomain (Coremail) with SMTP id AQAAf8AxBMUAZFBmZeoHAA--.10765S4; Fri, 24 May 2024 17:55:15 +0800 (CST) From: Hui Li To: gdb-patches@sourceware.org Cc: Tiezhu Yang Subject: [PATCH 2/2] gdb: LoongArch: Add support for hardware breakpoint Date: Fri, 24 May 2024 17:55:12 +0800 Message-Id: <20240524095512.16692-3-lihui@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20240524095512.16692-1-lihui@loongson.cn> References: <20240524095512.16692-1-lihui@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8AxBMUAZFBmZeoHAA--.10765S4 X-CM-SenderInfo: 5olk3xo6or00hjvr0hdfq/ X-Coremail-Antispam: 1Uk129KBj9fXoW3CF1rCw1kZF1ktrW8Aw18WFX_yoW8Wr1xZo WFyFZFgw18Gr1rK3yjyFn7XFyFvrs7CFW8Aw13Zwn8uan3try5XrWUKws8t34xXrs8W3y7 X348KasrJayxJF15l-sFpf9Il3svdjkaLaAFLSUrUUUUUb8apTn2vfkv8UJUUUU8wcxFpf 9Il3svdxBIdaVrneAqx4xG64xvF2IEw4CE5I8CrVC2j2WlIxkvb40E47kJYxn0WfASr-VF AUDa7-sFnT9fnUUIcSsGvfJTRUUUb4xYFVCjjxCrM7AC8VAFwI0_Jr0_Gr1l1xkIjI8I6I 8E6xAIw20EY4v20xvaj40_Wr0E3s1l1IIY67AEw4v_Jrv_JF1l8cAvFVAK0II2c7xJM28C jxkF64kEwVA0rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVWUJVWUCwA2z4x0Y4vE2Ix0cI 8IcVCY1x0267AKxVWUJVW8JwA2z4x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E 87Iv6xkF7I0E14v26r4UJVWxJr1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0c Ia020Ex4CE44I27wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jrv_ JF1lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwI xGrwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v2 6r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jrv_JF1lIxkvb4 0E47kJMIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY 6xkF7I0E14v26r1j6r4UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67 AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x 07b7zVbUUUUU= X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP, URIBL_SBL_A autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org LoongArch defines hardware watchpoint functions for fetch operations. After the software configures the watchpoints for fetch, the processor hardware will monitor the access addresses of the fetch operations and trigger a watchpoint exception when the watchpoint setting conditions are met. Hardware watchpoints for fetch operations is used to implement hardware breakpoint function on LoongArch. Refer to the following document for hardware breakpoint. https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#control-and-status-registers-related-to-watchpoints A simple test is as follows: lihui@bogon:~$ cat test.c #include int a = 0; int main() { printf("start test\n"); a = 1; printf("a = %d\n", a); printf("end test\n"); return 0; } lihui@bogon:~$ gcc -g test.c -o test without this patch: lihui@bogon:~$ gdb test ... (gdb) start ... Temporary breakpoint 1, main () at test.c:5 5 printf("start test\n"); (gdb) hbreak 8 No hardware breakpoint support in the target. with this patch: lihui@bogon:~$ gdb test ... (gdb) start ... Temporary breakpoint 1, main () at test.c:5 5 printf("start test\n"); (gdb) hbreak 8 Hardware assisted breakpoint 2 at 0x1200006ec: file test.c, line 8. (gdb) c Continuing. start test a = 1 Breakpoint 2, main () at test.c:8 8 printf("end test\n"); (gdb) c Continuing. end test [Inferior 1 (process 25378) exited normally] Signed-off-by: Hui Li --- gdb/loongarch-linux-nat.c | 74 +++++++++++++++++++++++++++++- gdb/nat/loongarch-hw-point.c | 37 +++++++++++++-- gdb/nat/loongarch-hw-point.h | 11 +++++ gdb/nat/loongarch-linux-hw-point.c | 51 ++++++++++++++------ gdb/nat/loongarch-linux-hw-point.h | 1 + gdb/nat/loongarch-linux.c | 21 +++++++-- include/elf/common.h | 2 + 7 files changed, 174 insertions(+), 23 deletions(-) diff --git a/gdb/loongarch-linux-nat.c b/gdb/loongarch-linux-nat.c index 9f5760066b3..873628775e2 100644 --- a/gdb/loongarch-linux-nat.c +++ b/gdb/loongarch-linux-nat.c @@ -54,6 +54,11 @@ class loongarch_linux_nat_target final : public linux_nat_trad_target bool stopped_by_watchpoint () override; bool stopped_data_address (CORE_ADDR *) override; + int insert_hw_breakpoint (struct gdbarch *gdbarch, + struct bp_target_info *bp_tgt) override; + int remove_hw_breakpoint (struct gdbarch *gdbarch, + struct bp_target_info *bp_tgt) override; + /* Override the GNU/Linux inferior startup hook. */ void post_startup_inferior (ptid_t) override; @@ -489,7 +494,8 @@ loongarch_linux_nat_target::can_use_hw_breakpoint (enum bptype type, int cnt, } else if (type == bp_hardware_breakpoint) { - return 0; + if (loongarch_num_bp_regs == 0) + return 0; } else gdb_assert_not_reached ("unexpected breakpoint type"); @@ -624,6 +630,72 @@ loongarch_linux_nat_target::stopped_by_watchpoint () return stopped_data_address (&addr); } +/* Insert a hardware-assisted breakpoint at BP_TGT->reqstd_address. + Return 0 on success, -1 on failure. */ + +int +loongarch_linux_nat_target::insert_hw_breakpoint (struct gdbarch *gdbarch, + struct bp_target_info *bp_tgt) +{ + int ret; + CORE_ADDR addr = bp_tgt->placed_address = bp_tgt->reqstd_address; + int len; + const enum target_hw_bp_type type = hw_execute; + struct loongarch_debug_reg_state *state + = loongarch_get_debug_reg_state (inferior_ptid.pid ()); + + gdbarch_breakpoint_from_pc (gdbarch, &addr, &len); + + if (show_debug_regs) + gdb_printf (gdb_stdlog, + "insert_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n", + (unsigned long) addr, len); + + ret = loongarch_handle_breakpoint (type, addr, len, 1 /* is_insert */, + inferior_ptid, state); + + if (show_debug_regs) + { + loongarch_show_debug_reg_state (state, + "insert_hw_breakpoint", addr, len, type); + } + + return ret; +} + +/* Remove a hardware-assisted breakpoint at BP_TGT->placed_address. + Return 0 on success, -1 on failure. */ + +int +loongarch_linux_nat_target::remove_hw_breakpoint (struct gdbarch *gdbarch, + struct bp_target_info *bp_tgt) +{ + int ret; + CORE_ADDR addr = bp_tgt->placed_address; + int len = 4; + const enum target_hw_bp_type type = hw_execute; + struct loongarch_debug_reg_state *state + = loongarch_get_debug_reg_state (inferior_ptid.pid ()); + + gdbarch_breakpoint_from_pc (gdbarch, &addr, &len); + + if (show_debug_regs) + gdb_printf (gdb_stdlog, + "remove_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n", + (unsigned long) addr, len); + + ret = loongarch_handle_breakpoint (type, addr, len, 0 /* is_insert */, + inferior_ptid, state); + + if (show_debug_regs) + { + loongarch_show_debug_reg_state (state, + "remove_hw_watchpoint", addr, len, type); + } + + return ret; +} + /* Implement the virtual inf_ptrace_target::post_startup_inferior method. */ void diff --git a/gdb/nat/loongarch-hw-point.c b/gdb/nat/loongarch-hw-point.c index 30c08dc498c..38e93e3cead 100644 --- a/gdb/nat/loongarch-hw-point.c +++ b/gdb/nat/loongarch-hw-point.c @@ -27,6 +27,7 @@ /* Number of hardware breakpoints/watchpoints the target supports. They are initialized with values obtained via ptrace. */ +int loongarch_num_bp_regs; int loongarch_num_wp_regs; /* Given the hardware breakpoint or watchpoint type TYPE and its @@ -112,7 +113,10 @@ loongarch_dr_state_insert_one_point (ptid_t ptid, } else { - return -1; + num_regs = loongarch_num_bp_regs; + dr_addr_p = state->dr_addr_bp; + dr_ctrl_p = state->dr_ctrl_bp; + dr_ref_count = state->dr_ref_count_bp; } ctrl = loongarch_point_encode_ctrl_reg (type, len); @@ -184,7 +188,10 @@ loongarch_dr_state_remove_one_point (ptid_t ptid, } else { - return -1; + num_regs = loongarch_num_bp_regs; + dr_addr_p = state->dr_addr_bp; + dr_ctrl_p = state->dr_ctrl_bp; + dr_ref_count = state->dr_ref_count_bp; } ctrl = loongarch_point_encode_ctrl_reg (type, len); @@ -214,6 +221,20 @@ loongarch_dr_state_remove_one_point (ptid_t ptid, return 0; } +int +loongarch_handle_breakpoint (enum target_hw_bp_type type, CORE_ADDR addr, + int len, int is_insert, ptid_t ptid, + struct loongarch_debug_reg_state *state) +{ + if (is_insert) + return loongarch_dr_state_insert_one_point (ptid, state, type, addr, + len, -1); + else + return loongarch_dr_state_remove_one_point (ptid, state, type, addr, + len, -1); +} + + int loongarch_handle_watchpoint (enum target_hw_bp_type type, CORE_ADDR addr, int len, int is_insert, ptid_t ptid, @@ -234,12 +255,12 @@ bool loongarch_any_set_debug_regs_state (loongarch_debug_reg_state *state, bool watchpoint) { - int count = watchpoint ? loongarch_num_wp_regs : 0; + int count = watchpoint ? loongarch_num_wp_regs : loongarch_num_bp_regs; if (count == 0) return false; - const CORE_ADDR *addr = watchpoint ? state->dr_addr_wp : 0; - const unsigned int *ctrl = watchpoint ? state->dr_ctrl_wp : 0; + const CORE_ADDR *addr = watchpoint ? state->dr_addr_wp : state->dr_addr_bp; + const unsigned int *ctrl = watchpoint ? state->dr_ctrl_wp : state->dr_ctrl_bp; for (int i = 0; i < count; i++) if (addr[i] != 0 || ctrl[i] != 0) @@ -268,6 +289,12 @@ loongarch_show_debug_reg_state (struct loongarch_debug_reg_state *state, : "??unknown??")))); debug_printf (":\n"); + debug_printf ("\tBREAKPOINTs:\n"); + for (i = 0; i < loongarch_num_bp_regs; i++) + debug_printf ("\tBP%d: addr=%s, ctrl=0x%08x, ref.count=%d\n", + i, core_addr_to_string_nz (state->dr_addr_bp[i]), + state->dr_ctrl_bp[i], state->dr_ref_count_bp[i]); + debug_printf ("\tWATCHPOINTs:\n"); for (i = 0; i < loongarch_num_wp_regs; i++) debug_printf ("\tWP%d: addr=%s, ctrl=0x%08x, ref.count=%d\n", diff --git a/gdb/nat/loongarch-hw-point.h b/gdb/nat/loongarch-hw-point.h index 69965ab2165..a05098b3ee1 100644 --- a/gdb/nat/loongarch-hw-point.h +++ b/gdb/nat/loongarch-hw-point.h @@ -33,6 +33,7 @@ Neither of these values may exceed the width of dr_changed_t measured in bits. */ +#define LOONGARCH_HBP_MAX_NUM 8 #define LOONGARCH_HWP_MAX_NUM 8 @@ -53,12 +54,18 @@ struct loongarch_debug_reg_state { + /* hardware breakpoint */ + CORE_ADDR dr_addr_bp[LOONGARCH_HBP_MAX_NUM]; + unsigned int dr_ctrl_bp[LOONGARCH_HBP_MAX_NUM]; + unsigned int dr_ref_count_bp[LOONGARCH_HBP_MAX_NUM]; + /* hardware watchpoint */ CORE_ADDR dr_addr_wp[LOONGARCH_HWP_MAX_NUM]; unsigned int dr_ctrl_wp[LOONGARCH_HWP_MAX_NUM]; unsigned int dr_ref_count_wp[LOONGARCH_HWP_MAX_NUM]; }; +extern int loongarch_num_bp_regs; extern int loongarch_num_wp_regs; /* Invoked when IDXth breakpoint/watchpoint register pair needs to be @@ -68,6 +75,10 @@ void loongarch_notify_debug_reg_change (ptid_t ptid, int is_watchpoint, unsigned int idx); +int loongarch_handle_breakpoint (enum target_hw_bp_type type, CORE_ADDR addr, + int len, int is_insert, ptid_t ptid, + struct loongarch_debug_reg_state *state); + int loongarch_handle_watchpoint (enum target_hw_bp_type type, CORE_ADDR addr, int len, int is_insert, ptid_t ptid, struct loongarch_debug_reg_state *state); diff --git a/gdb/nat/loongarch-linux-hw-point.c b/gdb/nat/loongarch-linux-hw-point.c index 14ed61f0825..a8aa9e6cd77 100644 --- a/gdb/nat/loongarch-linux-hw-point.c +++ b/gdb/nat/loongarch-linux-hw-point.c @@ -62,9 +62,6 @@ loongarch_dr_change_callback (struct lwp_info *lwp, int is_watchpoint, dr_changed_t *dr_changed_ptr; dr_changed_t dr_changed; - if (!is_watchpoint) - return -1; - if (info == NULL) { info = XCNEW (struct arch_lwp_info); @@ -74,14 +71,19 @@ loongarch_dr_change_callback (struct lwp_info *lwp, int is_watchpoint, if (show_debug_regs) { debug_printf ("loongarch_dr_change_callback: \n\tOn entry:\n"); - debug_printf ("\ttid%d, dr_changed_wp=0x%s\n", - tid, phex (info->dr_changed_wp, 8)); + debug_printf ("\ttid%d, dr_changed_bp=0x%s, " + "dr_changed_wp=0x%s\n", tid, + phex (info->dr_changed_bp, 8), + phex (info->dr_changed_wp, 8)); } - dr_changed_ptr = &info->dr_changed_wp; + dr_changed_ptr = is_watchpoint ? &info->dr_changed_wp + : &info->dr_changed_bp; dr_changed = *dr_changed_ptr; - gdb_assert (idx >= 0 && idx <= loongarch_num_wp_regs); + gdb_assert (idx >= 0 + && (idx <= (is_watchpoint ? loongarch_num_wp_regs + : loongarch_num_bp_regs))); /* The actual update is done later just before resuming the lwp, we just mark that one register pair needs updating. */ @@ -95,8 +97,10 @@ loongarch_dr_change_callback (struct lwp_info *lwp, int is_watchpoint, if (show_debug_regs) { - debug_printf ("\tOn exit:\n\ttid%d, dr_changed_wp=0x%s\n", - tid, phex (info->dr_changed_wp, 8)); + debug_printf ("\tOn exit:\n\ttid%d, dr_changed_bp=0x%s, " + "dr_changed_wp=0x%s\n", tid, + phex (info->dr_changed_bp, 8), + phex (info->dr_changed_wp, 8)); } return 0; @@ -136,9 +140,9 @@ loongarch_linux_set_debug_regs (struct loongarch_debug_reg_state *state, memset (®s, 0, sizeof (regs)); iov.iov_base = ®s; - count = watchpoint ? loongarch_num_wp_regs : 0; - addr = watchpoint ? state->dr_addr_wp : 0; - ctrl = watchpoint ? state->dr_ctrl_wp : 0; + count = watchpoint ? loongarch_num_wp_regs : loongarch_num_bp_regs; + addr = watchpoint ? state->dr_addr_wp : state->dr_addr_bp; + ctrl = watchpoint ? state->dr_ctrl_wp : state->dr_ctrl_bp; if (count == 0) return; @@ -151,7 +155,9 @@ loongarch_linux_set_debug_regs (struct loongarch_debug_reg_state *state, regs.dbg_regs[i].ctrl = ctrl[i]; } - if (ptrace(PTRACE_SETREGSET, tid, NT_LOONGARCH_HW_WATCH, (void *) &iov)) + if (ptrace(PTRACE_SETREGSET, tid, + watchpoint ? NT_LOONGARCH_HW_WATCH : NT_LOONGARCH_HW_BREAK, + (void *) &iov)) { if (errno == EINVAL) error (_("Invalid argument setting hardware debug registers")); @@ -194,6 +200,25 @@ loongarch_linux_get_debug_reg_capacity (int tid) loongarch_num_wp_regs = 0; } + /* Get hardware breakpoint register info. */ + result = ptrace (PTRACE_GETREGSET, tid, NT_LOONGARCH_HW_BREAK, &iov); + if ( result == 0) + { + loongarch_num_bp_regs = LOONGARCH_DEBUG_NUM_SLOTS (dreg_state.dbg_info); + if (loongarch_num_bp_regs > LOONGARCH_HBP_MAX_NUM) + { + warning (_("Unexpected number of hardware breakpoint registers" + " reported by ptrace, got %d, expected %d."), + loongarch_num_bp_regs, LOONGARCH_HBP_MAX_NUM); + loongarch_num_bp_regs = LOONGARCH_HBP_MAX_NUM; + } + } + else + { + warning (_("Unable to determine the number of hardware breakpoints" + " available.")); + loongarch_num_bp_regs = 0; + } } /* Return the debug register state for process PID. If no existing diff --git a/gdb/nat/loongarch-linux-hw-point.h b/gdb/nat/loongarch-linux-hw-point.h index 4086907e3c0..8d96443f5e0 100644 --- a/gdb/nat/loongarch-linux-hw-point.h +++ b/gdb/nat/loongarch-linux-hw-point.h @@ -93,6 +93,7 @@ struct arch_lwp_info /* When bit N is 1, it indicates the Nth hardware breakpoint or watchpoint register pair needs to be updated when the thread is resumed; see loongarch_linux_prepare_to_resume. */ + dr_changed_t dr_changed_bp; dr_changed_t dr_changed_wp; }; diff --git a/gdb/nat/loongarch-linux.c b/gdb/nat/loongarch-linux.c index 088d0fcbf34..03a0aaf9fd9 100644 --- a/gdb/nat/loongarch-linux.c +++ b/gdb/nat/loongarch-linux.c @@ -43,7 +43,8 @@ loongarch_linux_prepare_to_resume (struct lwp_info *lwp) if (info == NULL) return; - if (DR_HAS_CHANGED (info->dr_changed_wp)) + if (DR_HAS_CHANGED (info->dr_changed_bp) + || DR_HAS_CHANGED (info->dr_changed_wp)) { ptid_t ptid = ptid_of_lwp (lwp); int tid = ptid.lwp (); @@ -53,9 +54,19 @@ loongarch_linux_prepare_to_resume (struct lwp_info *lwp) if (show_debug_regs) debug_printf ("prepare_to_resume thread %d\n", tid); - loongarch_linux_set_debug_regs (state, tid, 1); - DR_CLEAR_CHANGED (info->dr_changed_wp); - + /* Watchpoints. */ + if (DR_HAS_CHANGED (info->dr_changed_wp)) + { + loongarch_linux_set_debug_regs (state, tid, 1); + DR_CLEAR_CHANGED (info->dr_changed_wp); + } + + /* Breakpoints. */ + if (DR_HAS_CHANGED (info->dr_changed_bp)) + { + loongarch_linux_set_debug_regs (state, tid, 0); + DR_CLEAR_CHANGED (info->dr_changed_bp); + } } } @@ -72,6 +83,8 @@ loongarch_linux_new_thread (struct lwp_info *lwp) /* If there are hardware breakpoints/watchpoints in the process then mark that all the hardware breakpoint/watchpoint register pairs for this thread need to be initialized (with data from arch_process_info.debug_reg_state). */ + if (loongarch_any_set_debug_regs_state (state, false)) + DR_MARK_ALL_CHANGED (info->dr_changed_bp, loongarch_num_bp_regs); if (loongarch_any_set_debug_regs_state (state, true)) DR_MARK_ALL_CHANGED (info->dr_changed_wp, loongarch_num_wp_regs); diff --git a/include/elf/common.h b/include/elf/common.h index f993146717c..91715490be3 100644 --- a/include/elf/common.h +++ b/include/elf/common.h @@ -720,6 +720,8 @@ /* note name must be "LINUX". */ #define NT_LARCH_LBT 0xa04 /* LoongArch Binary Translation registers */ /* note name must be "CORE". */ +#define NT_LOONGARCH_HW_BREAK 0xa05 /* LoongArch hardware breakpoint registers */ + /* note name must be "LINUX". */ #define NT_LOONGARCH_HW_WATCH 0xa06 /* LoongArch hardware watchpoint registers */ /* note name must be "LINUX". */ #define NT_RISCV_CSR 0x900 /* RISC-V Control and Status Registers */