From patchwork Thu May 23 13:48:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Willgerodt, Felix" X-Patchwork-Id: 90734 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C59EA38654A4 for ; Thu, 23 May 2024 13:50:11 +0000 (GMT) X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by sourceware.org (Postfix) with ESMTPS id 88FE43858415 for ; Thu, 23 May 2024 13:49:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 88FE43858415 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 88FE43858415 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=198.175.65.13 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1716472153; cv=none; b=p3ewfzd44a9E2uTkmcq/a2eogn/zQcGvzHWCF4tQfLOwHXoJxpxOAB3FFM0/ktExDE8mwHW9ELVSbI1iOsyv9EoVwgLiU1WaEmZ6i6T8FNwB55H4xpFQU798c6vPIqrx0txL46q4eCWUN9iOD5pY3vSaWhZQlHmaZPdFvh3Oswg= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1716472153; c=relaxed/simple; bh=z5gBrvmoJhAFF6O9jIiFKF5wzfkKMjCPOKcsrSgin0g=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=vJjyebbTbH/xeJOdqjm+mImgawxUoTWWDk4q0cZb2hOScEUq3aO28qxPIeQMa0cRt8lP+XvBxD1EToXmQ6qMOjaN//eqBTh9+1Xbb+hyqOx650f5KaEXbdNA5esHt4hc0dbjhJVlt2x8RvO9jAFgrauPmK5h8ArbptqKYnpFSb0= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716472151; x=1748008151; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=z5gBrvmoJhAFF6O9jIiFKF5wzfkKMjCPOKcsrSgin0g=; b=DjNW4nL+GeKHQw4WbU+eUBOHkC9gKpa/a4nRtoEgc60tT861ZICoXtol 2HUWwZ1Ka4dI8bah5ACvehj1h21jb7Add92Buv72kJJkf5wKnedN6sKW4 +jS+flg9Be/16HF0rSuQMDoOSDWEUn0LF5W4FE5BrPDG8rAfU6vvKwoWf H9S9v8WJdYTVNVz13pjiVGINXrFSNWkzf1Y7CjFgD6vjtzNdkMbXUfhJ/ EzX1k5PvDFwBf8UjDNBFUQajRCb7CtIa6ePrhXiurUf1VrqfNE1fC2Y/9 hbE6l7KfFwODvQsgyWc9P6pIl3WpNfeAH8RsjEt+uo/KRAZMggTO+HW5W A==; X-CSE-ConnectionGUID: z0wvBkGjSHmd9ro2MVds5g== X-CSE-MsgGUID: CfEDOqgyQEiAb/ChIGPS8A== X-IronPort-AV: E=McAfee;i="6600,9927,11081"; a="23923254" X-IronPort-AV: E=Sophos;i="6.08,182,1712646000"; d="scan'208";a="23923254" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 06:49:11 -0700 X-CSE-ConnectionGUID: 0yhlkZXkR06m9eKFdUATTQ== X-CSE-MsgGUID: RchaR44ISOObdqMc8tyMRw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,182,1712646000"; d="scan'208";a="33650319" Received: from gkldtt-dev-004.igk.intel.com (HELO localhost) ([10.123.221.202]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 06:49:09 -0700 From: Felix Willgerodt To: gdb-patches@sourceware.org Subject: [PATCH 3/3] gdb: rename offset to high bits in ymm registers Date: Thu, 23 May 2024 15:48:42 +0200 Message-Id: <20240523134842.3019820-4-felix.willgerodt@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240523134842.3019820-1-felix.willgerodt@intel.com> References: <20240523134842.3019820-1-felix.willgerodt@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org The xsave_ymm_avx512_offset data structure contains the xsave offset to the upper 128 bits of a ymm register. Similarly, for zmm this offset is described by xsave_avx512_zmm_h_offset, h indicating the high bits. This commit renames the xsave_ymm_avx512_offset to xsave_ymm_h_avx512_offset - as well as the associated define from XSAVE_YMM_AVX512_ADDR to XSAVE_YMM_H_AVX512_ADDR - to make this more consistent. Note, that the regnum defines already included the 'h' for ymm, like I387_YMM16H_REGNUM and I387_YMMH_AVX512_END_REGNUM. Co-authored-by: Nils-Christian Kempke --- gdb/i387-tdep.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/gdb/i387-tdep.c b/gdb/i387-tdep.c index 45bd43a50a9..675ee8d2e81 100644 --- a/gdb/i387-tdep.c +++ b/gdb/i387-tdep.c @@ -762,11 +762,11 @@ static int xsave_avxh_offset[] = (xsave + (tdep)->xsave_layout.avx_offset \ + xsave_avxh_offset[regnum - I387_YMM0H_REGNUM (tdep)]) -/* At xsave_ymm_avx512_offset[REGNUM] you'll find the relative offset +/* At xsave_ymm_h_avx512_offset[REGNUM] you'll find the relative offset within the ZMM region of the XSAVE extended state where the second 128bits of GDB register YMM16 + REGNUM is stored. */ -static int xsave_ymm_avx512_offset[] = +static int xsave_ymm_h_avx512_offset[] = { 16 + 0 * 64, /* %ymm16 through... */ 16 + 1 * 64, @@ -786,9 +786,9 @@ static int xsave_ymm_avx512_offset[] = 16 + 15 * 64 /* ... %ymm31 (128 bits each). */ }; -#define XSAVE_YMM_AVX512_ADDR(tdep, xsave, regnum) \ +#define XSAVE_YMM_H_AVX512_ADDR(tdep, xsave, regnum) \ (xsave + (tdep)->xsave_layout.zmm_offset \ - + xsave_ymm_avx512_offset[regnum - I387_YMM16H_REGNUM (tdep)]) + + xsave_ymm_h_avx512_offset[regnum - I387_YMM16H_REGNUM (tdep)]) /* At xsave_xmm_avx512_offset[REGNUM] you'll find the relative offset within the ZMM region of the XSAVE extended state where the first @@ -1187,7 +1187,7 @@ i387_supply_xsave (struct regcache *regcache, int regnum, regcache->raw_supply (regnum, zero); else regcache->raw_supply (regnum, - XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum)); + XSAVE_YMM_H_AVX512_ADDR (tdep, regs, regnum)); return; case avx512_xmm_avx512: @@ -1314,7 +1314,8 @@ i387_supply_xsave (struct regcache *regcache, int regnum, for (i = I387_YMM16H_REGNUM (tdep); i < I387_YMMH_AVX512_END_REGNUM (tdep); i++) - regcache->raw_supply (i, XSAVE_YMM_AVX512_ADDR (tdep, regs, i)); + regcache->raw_supply (i, + XSAVE_YMM_H_AVX512_ADDR (tdep, regs, i)); for (i = I387_XMM16_REGNUM (tdep); i < I387_XMM_AVX512_END_REGNUM (tdep); i++) @@ -1644,7 +1645,7 @@ i387_collect_xsave (const struct regcache *regcache, int regnum, memset (XSAVE_AVX512_ZMM16_H_ADDR (tdep, regs, i), 0, 32); for (i = I387_YMM16H_REGNUM (tdep); i < I387_YMMH_AVX512_END_REGNUM (tdep); i++) - memset (XSAVE_YMM_AVX512_ADDR (tdep, regs, i), 0, 16); + memset (XSAVE_YMM_H_AVX512_ADDR (tdep, regs, i), 0, 16); for (i = I387_XMM16_REGNUM (tdep); i < I387_XMM_AVX512_END_REGNUM (tdep); i++) memset (XSAVE_XMM_AVX512_ADDR (tdep, regs, i), 0, 16); @@ -1750,7 +1751,7 @@ i387_collect_xsave (const struct regcache *regcache, int regnum, i < I387_YMMH_AVX512_END_REGNUM (tdep); i++) { regcache->raw_collect (i, raw); - p = XSAVE_YMM_AVX512_ADDR (tdep, regs, i); + p = XSAVE_YMM_H_AVX512_ADDR (tdep, regs, i); if (memcmp (raw, p, 16) != 0) { xstate_bv |= X86_XSTATE_ZMM; @@ -1911,7 +1912,7 @@ i387_collect_xsave (const struct regcache *regcache, int regnum, case avx512_ymmh_avx512: /* This is an upper YMM16-31 register. */ - p = XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum); + p = XSAVE_YMM_H_AVX512_ADDR (tdep, regs, regnum); if (memcmp (raw, p, 16) != 0) { xstate_bv |= X86_XSTATE_ZMM;