From patchwork Tue May 21 20:27:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guinevere Larsen X-Patchwork-Id: 90635 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D52E0384AB72 for ; Tue, 21 May 2024 20:29:19 +0000 (GMT) X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by sourceware.org (Postfix) with ESMTPS id CAC2A3858D1E for ; Tue, 21 May 2024 20:28:43 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CAC2A3858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=redhat.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=redhat.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org CAC2A3858D1E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=170.10.129.124 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1716323325; cv=none; b=R/ouXPe/+F+eM+MtNINo1pK9BRtufjG0KtF1cM+hOWwh0FCS6r3Nwy7QvUuZArFqkQjMPDld9vRnXlQmDLmM3yXEGvkmX1mPuRo7zje30om79d7sd+TWpKeXM4rgpwqfwmV5xZlfcSe7JJKfitoy/zE2wu23k4LEHIqL/Bk3Z/Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1716323325; c=relaxed/simple; bh=IE+P4Fk9awTtC+Mff78laiOgbaXI/i3WZhaiSdfRjxk=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=afl5VXEJk7NU0fZT6BBCZKbOONNjAESU/WUhZLET+Xdk56WHargqMlkT4pqWrtDdRSMk5qz51+qkRzmrf/wu7EKm2Z3uqbM2p3/p1TTXPoMW/eQAWcsB29XvIRJaTdA4A+6slMpsZ3lhGWR5wPgNLw/kiLuXV5pvnb8sZ7wODV8= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1716323323; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+8NMai+lbtCyhEKI9bOJ4/P9PTm/1m9aPMwvhk4y7Vg=; b=KTtYD01NwhB/AMvEEwtGT8gm+rP7y8xm3IJCncvFTgKPGUC0KKuPbL0/5bhJ6bih95v59V 7j03UBKjKF06MvJ9vvA7p25CFCZ6OSF5n4mRsBE3kfYQSNHXNHfXJhlJZ4g7S3N3ii0wMI BmhrRc7FdEGgvFFivOmKyucsvc6iLDY= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-27-Xy-bWJQ4OV-on7adk-o96Q-1; Tue, 21 May 2024 16:28:41 -0400 X-MC-Unique: Xy-bWJQ4OV-on7adk-o96Q-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id E42478008A4 for ; Tue, 21 May 2024 20:28:40 +0000 (UTC) Received: from fedora.redhat.com (unknown [10.96.134.84]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 24E1A40004D; Tue, 21 May 2024 20:28:39 +0000 (UTC) From: Guinevere Larsen To: gdb-patches@sourceware.org Cc: Guinevere Larsen Subject: [PATCH 1/3] gdb: Start supporting AVX instruction Date: Tue, 21 May 2024 17:27:58 -0300 Message-ID: <20240521202800.2865871-2-blarsen@redhat.com> In-Reply-To: <20240521202800.2865871-1-blarsen@redhat.com> References: <20240521202800.2865871-1-blarsen@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.10 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org This patch introduces the information needed to properly identify the VEX prefix, used to signal an AVX and AVX2 instruction, and introduces a helper function to handle all AVX instruction, instead of adding to the 3000 line long recording function. The new helper also handles unsupported instructions so that the largest part of the i386_process_record doesn't have to be shifted by 2 spaces, which made an unreadably big patch file. The only expected difference added by this patch is a small change to the unsupported message. As a note for the future, we don't handle xmm16-31 and ymm16-31 because those require the EVEX prefix, meaning avx512 support. --- gdb/amd64-tdep.c | 3 +- gdb/i386-tdep.c | 91 ++++++++++++++++++++++++++++++++++++++++++++++-- gdb/i386-tdep.h | 2 ++ 3 files changed, 93 insertions(+), 3 deletions(-) diff --git a/gdb/amd64-tdep.c b/gdb/amd64-tdep.c index df6b882a3fb..27d6e20f90c 100644 --- a/gdb/amd64-tdep.c +++ b/gdb/amd64-tdep.c @@ -3134,7 +3134,8 @@ static const int amd64_record_regmap[] = AMD64_R8_REGNUM, AMD64_R9_REGNUM, AMD64_R10_REGNUM, AMD64_R11_REGNUM, AMD64_R12_REGNUM, AMD64_R13_REGNUM, AMD64_R14_REGNUM, AMD64_R15_REGNUM, AMD64_RIP_REGNUM, AMD64_EFLAGS_REGNUM, AMD64_CS_REGNUM, AMD64_SS_REGNUM, - AMD64_DS_REGNUM, AMD64_ES_REGNUM, AMD64_FS_REGNUM, AMD64_GS_REGNUM + AMD64_DS_REGNUM, AMD64_ES_REGNUM, AMD64_FS_REGNUM, AMD64_GS_REGNUM, + AMD64_XMM0_REGNUM, AMD64_YMM0H_REGNUM }; /* Implement the "in_indirect_branch_thunk" gdbarch function. */ diff --git a/gdb/i386-tdep.c b/gdb/i386-tdep.c index f1f909e1616..93a0926c4bc 100644 --- a/gdb/i386-tdep.c +++ b/gdb/i386-tdep.c @@ -4637,6 +4637,12 @@ struct i386_record_s int rip_offset; int popl_esp_hack; const int *regmap; + + /* These are used by VEX and XOP prefixes. */ + uint8_t map_select; + uint8_t vvvv; + uint8_t pp; + uint8_t l; }; /* Parse the "modrm" part of the memory address irp->addr points at. @@ -4975,6 +4981,31 @@ static int i386_record_floats (struct gdbarch *gdbarch, return 0; } +/* i386_process_record helper to deal with instructions that start + with VEX prefix. */ + +static bool +i386_record_vex (struct i386_record_s *ir, uint8_t rex_w, uint8_t rex_r, + int opcode, struct gdbarch *gdbarch) +{ + switch (opcode) + { + default: + gdb_printf (gdb_stderr, + _("Process record does not support VEX instruction 0x%02x " + "at address %s.\n"), + (unsigned int) (opcode), + paddress (gdbarch, ir->orig_addr)); + return -1; + } + + record_full_arch_list_add_reg (ir->regcache, ir->regmap[X86_RECORD_REIP_REGNUM]); + if (record_full_arch_list_add_end ()) + return -1; + + return 0; +} + /* Parse the current instruction, and record the values of the registers and memory that will be changed by the current instruction. Returns -1 if something goes wrong, 0 otherwise. */ @@ -4997,6 +5028,7 @@ i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, i386_gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); uint8_t rex_w = -1; uint8_t rex_r = 0; + bool vex_prefix = false; memset (&ir, 0, sizeof (struct i386_record_s)); ir.regcache = regcache; @@ -5082,6 +5114,53 @@ i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, else /* 32 bit target */ goto out_prefixes; break; + case 0xc4: /* 3-byte VEX prefixes (for AVX/AVX2 instructions). */ + { + /* The first byte just identifies the VEX prefix. Data is stored + on the following 2 bytes. */ + uint8_t byte; + if (record_read_memory (gdbarch, ir.addr, &byte, 1)) + return -1; + ir.addr++; + + rex_r = !((byte >> 7) & 0x1); + ir.rex_x = !((byte >> 6) & 0x1); + ir.rex_b = !((byte >> 5) & 0x1); + ir.map_select = byte & 0x1f; + /* Collect the last byte of the prefix. */ + if (record_read_memory (gdbarch, ir.addr, &byte, 1)) + return -1; + ir.addr++; + rex_w = (byte >> 7) & 0x1; + ir.vvvv = (~(byte >> 3) & 0xf); + ir.l = (byte >> 2) & 0x1; + ir.pp = byte & 0x3; + vex_prefix = true; + + break; + } + case 0xc5: /* 2-byte VEX prefix for AVX/AVX2 instructions. */ + { + /* The first byte just identifies the VEX prefix. Data is stored + on the following 2 bytes. */ + uint8_t byte; + if (record_read_memory (gdbarch, ir.addr, &byte, 1)) + return -1; + ir.addr++; + + /* On the 2-byte versions, these are pre-defined. */ + ir.rex_x = 0; + ir.rex_b = 0; + rex_w = 0; + ir.map_select = 1; + + rex_r = !((byte >> 7) & 0x1); + ir.vvvv = (~(byte >> 3) & 0xf); + ir.l = (byte >> 2) & 0x1; + ir.pp = byte & 0x3; + vex_prefix = true; + break; + } default: goto out_prefixes; break; @@ -5104,6 +5183,12 @@ i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, /* Now check op code. */ opcode = (uint32_t) opcode8; + if (vex_prefix) + { + /* If we found the VEX prefix, i386 will either record or warn that + the instruction isn't supported, so we can return the VEX result. */ + return i386_record_vex (&ir, rex_w, rex_r, opcode, gdbarch); + } reswitch: switch (opcode) { @@ -8088,9 +8173,11 @@ static const int i386_record_regmap[] = { I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM, I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM, - 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM, - I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM + I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM, + /* xmm0_regnum */ 0, I386_YMM0H_REGNUM }; /* Check that the given address appears suitable for a fast diff --git a/gdb/i386-tdep.h b/gdb/i386-tdep.h index a85e0a984a0..1f21f8de06c 100644 --- a/gdb/i386-tdep.h +++ b/gdb/i386-tdep.h @@ -339,6 +339,8 @@ enum record_i386_regnum X86_RECORD_ES_REGNUM, X86_RECORD_FS_REGNUM, X86_RECORD_GS_REGNUM, + X86_RECORD_XMM0_REGNUM, + X86_RECORD_YMM0H_REGNUM, }; #define I386_NUM_GREGS 16