From patchwork Mon Feb 26 14:26:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhushan Attarde X-Patchwork-Id: 86383 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8BBBC385829E for ; Mon, 26 Feb 2024 14:27:37 +0000 (GMT) X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from mx08-00376f01.pphosted.com (mx08-00376f01.pphosted.com [91.207.212.86]) by sourceware.org (Postfix) with ESMTPS id 917753858C55 for ; Mon, 26 Feb 2024 14:26:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 917753858C55 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=imgtec.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=imgtec.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 917753858C55 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=91.207.212.86 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1708957610; cv=none; b=KnFuHfvZGOdy9FbQrauGbAqmfgC5Jf7o0WZNnTi3S+Q7G1CHifs49FfYLVK9SWp+lER1hmHZU02zUk3hKegXmTxKBuQYURqoCnWv3I4A5UYuc6bzOsccWBiNeixMKEKFWw7PbkFM6G3tNfTaD9w9n44L8LfFg8+qfRvLWw6hHwM= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1708957610; c=relaxed/simple; bh=5FfjP2yV8M+rW2jBSUkJz2GZPr9ge3gdctwJ5cJ+I0E=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=mY4ZZo2x0dPXaJtnHNuz8ppcqkwKmRrlRU728GiGn9MWJVZXxnkPLMghTRGdn5gDaaG8X8u6AzMLG7vWa82hy+PuV1MsC80KZInebqEGiHwmJe1shQ5gYrc7TziOY1K0DmaC70cv7cBjJ1VKaE8WfJr4PbVIxzFdkReoY/Ukxgw= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from pps.filterd (m0168888.ppops.net [127.0.0.1]) by mx08-00376f01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 41Q86eF9005999; Mon, 26 Feb 2024 14:26:43 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=imgtec.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= dk201812; bh=DEhc93K/fSE+h0AHHjPyqDxTCebbJV7jw4R1ePcXPco=; b=tuB Z9PmzmI+tWfgOHLXDWiQ153RuBMHSCF9TOjGLBByLmR/SqDOnn+h0j/HqxbE3vv4 JNBjUO2cxpUKCUni2KlSpfWO01otdEr5KmlQUScpAnpJMt1TSM626udmffYnFqOb Fhd5okr8apl3eiP7o1HiE6XzI6UJzTzgCbq6pGSZujMYG+YLxyNT32lzy8pAF29U G1zHN3XUR2TiI2ZdAu29wQiuJsr++Ckll7o2LAfUvgwbRph8aKIPTxdOKnXTaV+h PFKK72XW9qiTVGzTBM6IVokZ2hHC0HJ1jqUQ83CqYKX/wNxdB+n4DtnLvQXfnrae 2nbHCwO9W+6+RwNqmqg== Received: from hhmail05.hh.imgtec.org ([217.156.249.195]) by mx08-00376f01.pphosted.com (PPS) with ESMTPS id 3wf7kssr69-5 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Mon, 26 Feb 2024 14:26:43 +0000 (GMT) Received: from hhbattarde.hh.imgtec.org (10.100.136.78) by HHMAIL05.hh.imgtec.org (10.100.10.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 26 Feb 2024 14:26:42 +0000 From: To: CC: , , , Bhushan Attarde Subject: [PATCH 08/11] sim: riscv: Add double precision floating-point sign-injection, min and max instructions Date: Mon, 26 Feb 2024 14:26:25 +0000 Message-ID: <20240226142628.1629048-5-bhushan.attarde@imgtec.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240226142628.1629048-1-bhushan.attarde@imgtec.com> References: <20240226142628.1629048-1-bhushan.attarde@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [10.100.136.78] X-ClientProxiedBy: HHMAIL05.hh.imgtec.org (10.100.10.120) To HHMAIL05.hh.imgtec.org (10.100.10.120) X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Proofpoint-GUID: Lkb1YKxGdDm28Kdcd0w4sY1aUWwZB8vN X-Proofpoint-ORIG-GUID: Lkb1YKxGdDm28Kdcd0w4sY1aUWwZB8vN X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org From: Bhushan Attarde Added simulation of following single precision floating-point instructions fsgnjn.d, fsgnjx.d, fmin.d and fmax.d. Updated test file d-fp-compare.s and added d-fp-sign-inject.s in sim/testsuite/riscv/ to test these instructions. --- sim/riscv/sim-main.c | 65 +++++++++++++++++++ sim/testsuite/riscv/d-fp-compare.s | 22 +++++++ sim/testsuite/riscv/d-fp-sign-inject.s | 87 ++++++++++++++++++++++++++ 3 files changed, 174 insertions(+) create mode 100644 sim/testsuite/riscv/d-fp-sign-inject.s diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c index 4313516b8b7..4f347fbfc5e 100644 --- a/sim/riscv/sim-main.c +++ b/sim/riscv/sim-main.c @@ -1359,6 +1359,40 @@ float64_compare (SIM_CPU *cpu, int rd, int rs1, int rs2, int flags) } } +/* Handle double precision floating point math instructions. */ +static void +float64_math (SIM_CPU *cpu, int rd, int rs1, int rs2, int flags) +{ + struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu); + double a, b, result = 0; + uint64_t rs1_bits, rs2_bits, rd_bits; + const char *frd_name = riscv_fpr_names_abi[rd]; + const char *frs1_name = riscv_fpr_names_abi[rs1]; + const char *frs2_name = riscv_fpr_names_abi[rs2]; + + rs1_bits = (uint64_t) riscv_cpu->fpregs[rs1]; + memcpy (&a, &rs1_bits, sizeof (a)); + rs2_bits = (uint64_t) riscv_cpu->fpregs[rs2]; + memcpy (&b, &rs2_bits, sizeof (b)); + + switch (flags) + { + case FMAX: + TRACE_INSN (cpu, "fmax.d %s, %s, %s;", frd_name, frs1_name, frs2_name); + result = fmax (a, b); + break; + case FMIN: + TRACE_INSN (cpu, "fmin.d %s, %s, %s;", frd_name, frs1_name, frs2_name); + result = fmin (a, b); + break; + } + + /* Store result. */ + memcpy (&rd_bits, &result, sizeof (result)); + store_fp (cpu, rd, rd_bits); + +} + /* Simulate single precision floating point instructions. */ static sim_cia execute_f (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) @@ -1668,6 +1702,37 @@ execute_d (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) store_fp (cpu, rd, rs1_bits); break; } + case MATCH_FSGNJN_D: + { + uint64_t rs1_bits, rs2_bits; + TRACE_INSN (cpu, "fsgnjn.d %s, %s, %s;", frd_name, frs1_name, + frs2_name); + rs1_bits = (uint64_t) riscv_cpu->fpregs[rs1]; + rs2_bits = ~((uint64_t) riscv_cpu->fpregs[rs2]); + rs1_bits = (rs2_bits & 0x8000000000000000ull) + | (rs1_bits & 0x7fffffffffffffffull); + store_fp (cpu, rd, rs1_bits); + break; + } + case MATCH_FSGNJX_D: + { + uint64_t rs1_bits, rs2_bits; + TRACE_INSN (cpu, "fsgnjx.d %s, %s, %s;", frd_name, frs1_name, + frs2_name); + rs1_bits = (uint64_t) riscv_cpu->fpregs[rs1]; + rs2_bits = (uint64_t) riscv_cpu->fpregs[rs2]; + rs1_bits = ((rs1_bits & 0x8000000000000000ull) + ^ (rs2_bits & 0x8000000000000000ull)) + | (rs1_bits & 0x7fffffffffffffffull); + store_fp (cpu, rd, rs1_bits); + break; + } + case MATCH_FMIN_D: + float64_math (cpu, rd, rs1, rs2, FMIN); + break; + case MATCH_FMAX_D: + float64_math (cpu, rd, rs1, rs2, FMAX); + break; default: TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name); sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled, SIM_SIGILL); diff --git a/sim/testsuite/riscv/d-fp-compare.s b/sim/testsuite/riscv/d-fp-compare.s index 0e168fed9de..1a926211216 100755 --- a/sim/testsuite/riscv/d-fp-compare.s +++ b/sim/testsuite/riscv/d-fp-compare.s @@ -20,11 +20,16 @@ _arg2: .double 0.5 .double 2.2 +_expected: + .double 0.5 + .double 2.2 + start .option push .option norelax la a0,_arg1 la a1,_arg2 + la a2,_expected li a3,1 .option pop @@ -65,6 +70,23 @@ _arg2: fclass.d a4,fa0 bne a3,a4,test_fail + # Test fmin.d instruction. + fld fa0,0(a0) + fld fa1,8(a1) + fld fa2,0(a2) + fmin.d fa3,fa0,fa1 + feq.d a4,fa3,fa2 + li a3,1 + bne a4,a3,test_fail + + # Test fmax.d instruction. + fld fa0,0(a0) + fld fa1,8(a1) + fld fa2,8(a2) + fmax.d fa3,fa0,fa1 + feq.d a4,fa3,fa2 + bne a4,a3,test_fail + test_pass: pass diff --git a/sim/testsuite/riscv/d-fp-sign-inject.s b/sim/testsuite/riscv/d-fp-sign-inject.s new file mode 100644 index 00000000000..c2f61ba3cdd --- /dev/null +++ b/sim/testsuite/riscv/d-fp-sign-inject.s @@ -0,0 +1,87 @@ +# Double precision sign-injection instructions. +# mach: riscv64 +# sim(riscv64): --model RV64ID +# ld(riscv64): -m elf64lriscv +# as(riscv64): -march=rv64id + +.include "testutils.inc" + + .section .data + .align 3 + +_arg1: + .double 2.0 + .double -2.0 + +_arg2: + .double 1.0 + .double -1.0 + +_expected: + .double 2.0 + .double -2.0 + + start + .option push + .option norelax + la a0,_arg1 + la a1,_arg2 + la a2,_expected + li a3,1 + .option pop + + # Test fsgnj.d instruction. + fld fa0,0(a0) + fld fa1,0(a1) + fld fa2,0(a2) + fsgnj.d fa3,fa0,fa1 + feq.d a4,fa3,fa2 + bne a4,a3,test_fail + fld fa1,8(a1) + fld fa2,8(a2) + fsgnj.d fa3,fa0,fa1 + feq.d a4,fa3,fa2 + bne a4,a3,test_fail + + # Test fsgnjn.d (fneg.d) instruction. + fld fa0,0(a0) + fld fa1,0(a1) + fld fa2,8(a2) + fsgnjn.d fa3,fa0,fa1 + feq.d a4,fa3,fa2 + bne a4,a3,test_fail + fld fa1,8(a1) + fld fa2,0(a2) + fsgnjn.d fa3,fa0,fa1 + feq.d a4,fa3,fa2 + bne a4,a3,test_fail + fld fa0,0(a0) + fld fa2,8(a2) + fneg.d fa3,fa0 + feq.d a4,fa3,fa2 + bne a4,a3,test_fail + + # Test fsgnjx.d (fabs.d) instruction. + fld fa0,0(a0) + fld fa1,8(a1) + fld fa2,8(a2) + fsgnjx.d fa3,fa0,fa1 + feq.d a4,fa3,fa2 + bne a4,a3,test_fail + fld fa0,8(a0) + fld fa1,8(a1) + fld fa2,0(a2) + fsgnjx.d fa3,fa0,fa1 + feq.d a4,fa3,fa2 + bne a4,a3,test_fail + fld fa0,8(a0) + fld fa2,0(a2) + fabs.d fa3,fa0 + feq.d a4,fa3,fa2 + bne a4,a3,test_fail + +test_pass: + pass + +test_fail: + fail