From patchwork Mon Feb 26 14:22:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhushan Attarde X-Patchwork-Id: 86380 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 53BEE3858409 for ; Mon, 26 Feb 2024 14:25:11 +0000 (GMT) X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from mx08-00376f01.pphosted.com (mx08-00376f01.pphosted.com [91.207.212.86]) by sourceware.org (Postfix) with ESMTPS id E455A3858432 for ; Mon, 26 Feb 2024 14:23:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E455A3858432 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=imgtec.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=imgtec.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org E455A3858432 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=91.207.212.86 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1708957385; cv=none; b=DCTtaPoSQy6XsQh2Pp9wp0IABHHHXZJF+iQCtxKgL37vlwMl4L6KRAMYTTkunwdA5SfmToPhDsjyldt7gd3NZf8YiR8AWu9BmyFRPHIcS6rA6hwi/4zzupceMqaGSQzczX7zvicPBgx/nbJ8aZ9PKBJd2egEOeslyYQgmpZmWb8= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1708957385; c=relaxed/simple; bh=1gu19hOOl9a1hUJ4poTKqXe9j3GaXrnjZE0nxiP+46c=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=HCspOZd3cpyn4BT8xchopSMXR9Q7bYkCHXj6EBHrQTOGTRQd7NkMO0Kq/NKbvFk08WyVvd5scyReIG0ApPrbk0Wxu8YN9rxIt+SYxqUfmYGQR2B1JYtgXcAAD9Hjjbr3ICDwDbisDd+36IcuoHFZEk4WESPP8f+U/x7ocwr2VDQ= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from pps.filterd (m0168888.ppops.net [127.0.0.1]) by mx08-00376f01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 41Q8CPdJ013671; Mon, 26 Feb 2024 14:22:50 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=imgtec.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= dk201812; bh=NyU3Gh+LoVmr6MJOBTRqKdZrVn2Tq3XVkAvqMP75ZcU=; b=w2f m1osseK0MBuhrlyuFnGCcpo6oVES+8qmDw4WCgyMowSZARQyP49772UfIyjUbJM+ ESHqDkQ1Ksv4gA6buiJOw/y2vMkHHBlKJWBp3WNNYvtjhkxC6VoWb6rEexe1t835 FIfFFmHBFULNVVFImkNNgVa8Z0/u1fu+nyES3EMivaKkbrp/1i3X7H4TMZPCkkq3 KsD9NLQIogTO6wMT4ZT7Xj9hhw5lxaw9p4ikfwieZs+2o1n6jhQpRxhYGWmOuOa5 Dz+e3yIWEuT+PAbYkFJc+XoTEEFxSzurX5IWp0JZ5ikfG49vAgfy5TTBvhBEC/3X vLIZCIlnDc08O3zs/Yg== Received: from hhmail05.hh.imgtec.org ([217.156.249.195]) by mx08-00376f01.pphosted.com (PPS) with ESMTPS id 3wf7kssr3e-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Mon, 26 Feb 2024 14:22:50 +0000 (GMT) Received: from hhbattarde.hh.imgtec.org (10.100.136.78) by HHMAIL05.hh.imgtec.org (10.100.10.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 26 Feb 2024 14:22:48 +0000 From: To: CC: , , , Bhushan Attarde Subject: [PATCH 02/11] sim: riscv: Add single precision floating-point sign injection, min and max instructions Date: Mon, 26 Feb 2024 14:22:25 +0000 Message-ID: <20240226142234.1628932-3-bhushan.attarde@imgtec.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240226142234.1628932-1-bhushan.attarde@imgtec.com> References: <20240226142234.1628932-1-bhushan.attarde@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [10.100.136.78] X-ClientProxiedBy: HHMAIL05.hh.imgtec.org (10.100.10.120) To HHMAIL05.hh.imgtec.org (10.100.10.120) X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Proofpoint-GUID: lPwOXfOzb0FYuxxrN3paqxqLKV8Y1GJ1 X-Proofpoint-ORIG-GUID: lPwOXfOzb0FYuxxrN3paqxqLKV8Y1GJ1 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org From: Bhushan Attarde Added simulation of following single precision floating-point instructions sgnjn.s (fneg.s), fsgnjx.s (fabs.s), fmin.s and fmax.s. Updated test files s-fp-compare.s and s-fp-sign-inject.s in sim/testsuite/riscv/ to test these instructions --- sim/riscv/sim-main.c | 64 ++++++++++++++++++++++++++ sim/testsuite/riscv/s-fp-compare.s | 22 +++++++++ sim/testsuite/riscv/s-fp-sign-inject.s | 38 +++++++++++++++ 3 files changed, 124 insertions(+) diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c index d3a07585944..9c132d9a448 100644 --- a/sim/riscv/sim-main.c +++ b/sim/riscv/sim-main.c @@ -75,6 +75,8 @@ static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1]; #define FLT 2 #define FLE 3 #define FCLASS 4 +#define FMIN 5 +#define FMAX 6 static INLINE void store_rd (SIM_CPU *cpu, int rd, unsigned_word val) @@ -810,6 +812,39 @@ float32_compare (SIM_CPU *cpu, int rd, int rs1, int rs2, int flags) } } +/* Handle single precision floating point math instructions. */ +static void +float32_math (SIM_CPU *cpu, int rd, int rs1, int rs2, int flags) +{ + struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu); + float a, b, result = 0; + uint32_t rs1_bits, rs2_bits, rd_bits; + const char *frd_name = riscv_fpr_names_abi[rd]; + const char *frs1_name = riscv_fpr_names_abi[rs1]; + const char *frs2_name = riscv_fpr_names_abi[rs2]; + + rs1_bits = (uint32_t) riscv_cpu->fpregs[rs1]; + memcpy (&a, &rs1_bits, sizeof (a)); + rs2_bits = (uint32_t) riscv_cpu->fpregs[rs2]; + memcpy (&b, &rs2_bits, sizeof (b)); + + switch (flags) + { + case FMAX: + TRACE_INSN (cpu, "fmax.s %s, %s, %s;", frd_name, frs1_name, frs2_name); + result = fmaxf (a, b); + break; + case FMIN: + TRACE_INSN (cpu, "fmin.s %s, %s, %s;", frd_name, frs1_name, frs2_name); + result = fminf (a, b); + break; + } + + /* Store result. */ + memcpy (&rd_bits, &result, sizeof (result)); + store_fp (cpu, rd, rd_bits); +} + /* Simulate single precision floating point instructions. */ static sim_cia execute_f (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) @@ -885,6 +920,35 @@ execute_f (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) case MATCH_FCLASS_S: float32_compare (cpu, rd, rs1, 0, FCLASS); break; + case MATCH_FSGNJN_S: + { + uint32_t rs1_bits, rs2_bits; + TRACE_INSN (cpu, "fsgnjn.s %s, %s, %s;", frd_name, frs1_name, + frs2_name); + rs1_bits = (uint32_t) riscv_cpu->fpregs[rs1]; + rs2_bits = ~((uint32_t) riscv_cpu->fpregs[rs2]); + rs1_bits = (rs2_bits & 0x80000000) | (rs1_bits & 0x7fffffff); + store_fp (cpu, rd, rs1_bits); + break; + } + case MATCH_FSGNJX_S: + { + uint32_t rs1_bits, rs2_bits; + TRACE_INSN (cpu, "fsgnjx.s %s, %s, %s;", frd_name, frs1_name, + frs2_name); + rs1_bits = (uint32_t) riscv_cpu->fpregs[rs1]; + rs2_bits = (uint32_t) riscv_cpu->fpregs[rs2]; + rs1_bits = ((rs1_bits & 0x80000000) ^ (rs2_bits & 0x80000000)) + | (rs1_bits & 0x7fffffff); + store_fp (cpu, rd, rs1_bits); + break; + } + case MATCH_FMIN_S: + float32_math (cpu, rd, rs1, rs2, FMIN); + break; + case MATCH_FMAX_S: + float32_math (cpu, rd, rs1, rs2, FMAX); + break; default: TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name); sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled, SIM_SIGILL); diff --git a/sim/testsuite/riscv/s-fp-compare.s b/sim/testsuite/riscv/s-fp-compare.s index d5b98b30233..7aef3ce51c2 100644 --- a/sim/testsuite/riscv/s-fp-compare.s +++ b/sim/testsuite/riscv/s-fp-compare.s @@ -23,11 +23,16 @@ _arg2: .float 0.5 .float 2.2 +_expected: + .float 0.5 + .float 2.2 + start .option push .option norelax la a0,_arg1 la a1,_arg2 + la a2,_expected li a3,1 .option pop @@ -68,6 +73,23 @@ _arg2: fclass.s a4,fa0 bne a3,a4,test_fail + # Test fmin.s instruction. + flw fa0,0(a0) + flw fa1,4(a1) + flw fa2,0(a2) + fmin.s fa3,fa0,fa1 + feq.s a4,fa3,fa2 + li a3,1 + bne a4,a3,test_fail + + # Test fmax.s instruction. + flw fa0,0(a0) + flw fa1,4(a1) + flw fa2,4(a2) + fmax.s fa3,fa0,fa1 + feq.s a4,fa3,fa2 + bne a4,a3,test_fail + test_pass: pass diff --git a/sim/testsuite/riscv/s-fp-sign-inject.s b/sim/testsuite/riscv/s-fp-sign-inject.s index 733756a2197..e4efbaaf29e 100644 --- a/sim/testsuite/riscv/s-fp-sign-inject.s +++ b/sim/testsuite/riscv/s-fp-sign-inject.s @@ -14,6 +14,7 @@ _arg1: .float 2.0 + .float -2.0 _arg2: .float 1.0 @@ -45,6 +46,43 @@ _expected: feq.s a4,fa3,fa2 bne a4,a3,test_fail + # Test fsgnjn.s (fneg.s) instruction. + flw fa0,0(a0) + flw fa1,0(a1) + flw fa2,4(a2) + fsgnjn.s fa3,fa0,fa1 + feq.s a4,fa3,fa2 + bne a4,a3,test_fail + flw fa1,4(a1) + flw fa2,0(a2) + fsgnjn.s fa3,fa0,fa1 + feq.s a4,fa3,fa2 + bne a4,a3,test_fail + flw fa0,0(a0) + flw fa2,4(a2) + fneg.s fa3,fa0 + feq.s a4,fa3,fa2 + bne a4,a3,test_fail + + # Test fsgnjx.s (fabs.s) instruction. + flw fa0,0(a0) + flw fa1,4(a1) + flw fa2,4(a2) + fsgnjx.s fa3,fa0,fa1 + feq.s a4,fa3,fa2 + bne a4,a3,test_fail + flw fa0,4(a0) + flw fa1,4(a1) + flw fa2,0(a2) + fsgnjx.s fa3,fa0,fa1 + feq.s a4,fa3,fa2 + bne a4,a3,test_fail + flw fa0,4(a0) + flw fa2,0(a2) + fabs.s fa3,fa0 + feq.s a4,fa3,fa2 + bne a4,a3,test_fail + test_pass: pass