From patchwork Fri Dec 22 15:54:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Frysinger X-Patchwork-Id: 82766 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 883D53858C2F for ; Fri, 22 Dec 2023 15:55:24 +0000 (GMT) X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from smtp.gentoo.org (smtp.gentoo.org [IPv6:2001:470:ea4a:1:5054:ff:fec7:86e4]) by sourceware.org (Postfix) with ESMTP id E9D123858D28 for ; Fri, 22 Dec 2023 15:55:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E9D123858D28 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gentoo.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gentoo.org ARC-Filter: OpenARC Filter v1.0.0 sourceware.org E9D123858D28 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2001:470:ea4a:1:5054:ff:fec7:86e4 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703260506; cv=none; b=O6V+1pWRlWGoKNpGpRwnGpmN+jaaHwUpG1U8eQnN/pi37KPVr0btquGZs+nv3DalP+gJYEUja7IFNYpd9wij/Ol8IYcT0Ii/CxAhIhdSkDyVtdr5wXKXavCu8RMZEPV4t6yDYNjbjHvNCdht0/sqDftFRwAq/pjsMwlRggC4BjQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703260506; c=relaxed/simple; bh=/eJoaeACRrCWlIA9Md9/QawhVLVwTCRH+QDeUqNXDyY=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=wNfdmgDDi1xVyZCYk1coL1GikxRayVf3Jdb9skig3N/ERJ3p2ZGYYdOKxBR1IyhDWx+kkriEk/Q/7HC9BORq6VDUzB07Zp2CJgXjV3l4Uv2I8LhpxFPqRVnD0QQ5fNo+eOgXOD/JM5kSgABLzbwJGML5uU9DHBVF3oXgtpFOQU8= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by smtp.gentoo.org (Postfix, from userid 559) id 81AE933E02F; Fri, 22 Dec 2023 15:55:00 +0000 (UTC) From: Mike Frysinger To: gdb-patches@sourceware.org Subject: [PATCH/committed] sim: cgen: regenerate decode tables to avoid shadow warnings Date: Fri, 22 Dec 2023 10:54:57 -0500 Message-ID: <20231222155457.23372-1-vapier@gentoo.org> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org Use latest cgen to regenerate the decode tables which has some shadow warning fixes with "val" variables. --- sim/cris/decodev10.c | 292 +++++++++++++++++++++---------------------- sim/cris/decodev32.c | 228 ++++++++++++++++----------------- sim/frv/decode.c | 292 +++++++++++++++++++++---------------------- sim/iq2000/decode.c | 56 ++++----- sim/lm32/decode.c | 8 +- sim/m32r/decode.c | 28 ++--- sim/m32r/decode2.c | 52 ++++---- sim/m32r/decodex.c | 40 +++--- sim/or1k/decode.c | 100 +++++++-------- 9 files changed, 548 insertions(+), 548 deletions(-) diff --git a/sim/cris/decodev10.c b/sim/cris/decodev10.c index 7afcddf5b903..650c5db0b59a 100644 --- a/sim/cris/decodev10.c +++ b/sim/cris/decodev10.c @@ -328,8 +328,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, CGEN_INSN_WORD insn = base_insn; { - unsigned int val = (((insn >> 4) & (255 << 0))); - switch (val) + unsigned int val0 = (((insn >> 4) & (255 << 0))); + switch (val0) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -348,8 +348,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, case 14 : /* fall through */ case 15 : { - unsigned int val = (((insn >> 12) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 12) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -387,8 +387,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, case 30 : /* fall through */ case 31 : { - unsigned int val = (((insn >> 12) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 12) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -459,8 +459,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, case 79 : itype = CRISV10F_INSN_BTST; goto extract_sfmt_btst; case 80 : { - unsigned int val = (((insn >> 8) & (7 << 4)) | ((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 8) & (7 << 4)) | ((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -591,8 +591,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, case 127 : itype = CRISV10F_INSN_ADDI_B_R; goto extract_sfmt_addi_b_r; case 15 : { - unsigned int val = (((insn >> 15) & (1 << 0))); - switch (val) + unsigned int val2 = (((insn >> 15) & (1 << 0))); + switch (val2) { case 0 : itype = CRISV10F_INSN_NOP; goto extract_sfmt_nop; case 1 : itype = CRISV10F_INSN_ADDI_B_R; goto extract_sfmt_addi_b_r; @@ -607,8 +607,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, case 83 : itype = CRISV10F_INSN_SCC; goto extract_sfmt_scc; case 84 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -631,8 +631,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 85 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -655,8 +655,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 86 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -693,8 +693,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, case 101 : itype = CRISV10F_INSN_MOVE_W_R; goto extract_sfmt_move_b_r; case 102 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -717,8 +717,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 103 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -768,8 +768,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, case 130 : itype = CRISV10F_INSN_ADDS_M_B_M; goto extract_sfmt_adds_m_b_m; case 131 : { - unsigned int val = (((insn >> 8) & (7 << 4)) | ((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 8) & (7 << 4)) | ((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -900,8 +900,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, case 126 : itype = CRISV10F_INSN_ADDS_M_W_M; goto extract_sfmt_adds_m_w_m; case 127 : { - unsigned int val = (((insn >> 15) & (1 << 0))); - switch (val) + unsigned int val2 = (((insn >> 15) & (1 << 0))); + switch (val2) { case 0 : itype = CRISV10F_INSN_ADDS_M_W_M; goto extract_sfmt_adds_m_w_m; case 1 : itype = CRISV10F_INSN_ADDSPCPC; goto extract_sfmt_addspcpc; @@ -928,8 +928,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, case 146 : itype = CRISV10F_INSN_MULU_D; goto extract_sfmt_muls_b; case 147 : { - unsigned int val = (((insn >> 12) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 12) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1005,8 +1005,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, case 187 : /* fall through */ case 251 : { - unsigned int val = (((insn >> 12) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 12) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1037,8 +1037,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, case 255 : itype = CRISV10F_INSN_MOVEM_R_M; goto extract_sfmt_movem_r_m; case 192 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1061,8 +1061,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 193 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1085,8 +1085,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 194 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1109,8 +1109,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 195 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1133,8 +1133,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 196 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1157,8 +1157,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 197 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1181,8 +1181,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 198 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1205,8 +1205,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 199 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1229,8 +1229,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 200 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1253,8 +1253,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 201 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1277,8 +1277,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 202 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1301,8 +1301,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 203 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1325,8 +1325,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 204 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1349,8 +1349,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 205 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1373,8 +1373,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 206 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1397,8 +1397,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 207 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1424,8 +1424,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, case 210 : itype = CRISV10F_INSN_MULS_D; goto extract_sfmt_muls_b; case 211 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1448,8 +1448,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 212 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1472,8 +1472,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 213 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1496,8 +1496,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 214 : { - unsigned int val = (((insn >> 12) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 12) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1515,8 +1515,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, case 13 : /* fall through */ case 14 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val2 = (((insn >> 0) & (15 << 0))); + switch (val2) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1539,8 +1539,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 15 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val2 = (((insn >> 0) & (15 << 0))); + switch (val2) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1566,8 +1566,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 215 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1596,8 +1596,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 220 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1620,8 +1620,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 221 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1644,8 +1644,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 222 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1668,8 +1668,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 223 : { - unsigned int val = (((insn >> 12) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 12) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1698,8 +1698,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 224 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1722,8 +1722,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 225 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1746,8 +1746,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 226 : { - unsigned int val = (((insn >> 12) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 12) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1765,8 +1765,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, case 13 : /* fall through */ case 14 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val2 = (((insn >> 0) & (15 << 0))); + switch (val2) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1789,8 +1789,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 15 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val2 = (((insn >> 0) & (15 << 0))); + switch (val2) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1816,8 +1816,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 227 : { - unsigned int val = (((insn >> 11) & (15 << 1)) | ((insn >> 0) & (1 << 0))); - switch (val) + unsigned int val1 = (((insn >> 11) & (15 << 1)) | ((insn >> 0) & (1 << 0))); + switch (val1) { case 0 : /* fall through */ case 2 : /* fall through */ @@ -1842,8 +1842,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, case 30 : itype = CRISV10F_INSN_MOVE_M_SPRV10; goto extract_sfmt_move_m_sprv10; case 1 : { - unsigned int val = (((insn >> 1) & (7 << 0))); - switch (val) + unsigned int val2 = (((insn >> 1) & (7 << 0))); + switch (val2) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1858,8 +1858,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 11 : { - unsigned int val = (((insn >> 1) & (7 << 0))); - switch (val) + unsigned int val2 = (((insn >> 1) & (7 << 0))); + switch (val2) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1874,8 +1874,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 15 : { - unsigned int val = (((insn >> 1) & (7 << 0))); - switch (val) + unsigned int val2 = (((insn >> 1) & (7 << 0))); + switch (val2) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1890,8 +1890,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 16 : { - unsigned int val = (((insn >> 1) & (7 << 0))); - switch (val) + unsigned int val2 = (((insn >> 1) & (7 << 0))); + switch (val2) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1906,8 +1906,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 19 : { - unsigned int val = (((insn >> 1) & (7 << 0))); - switch (val) + unsigned int val2 = (((insn >> 1) & (7 << 0))); + switch (val2) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1922,8 +1922,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 21 : { - unsigned int val = (((insn >> 1) & (7 << 0))); - switch (val) + unsigned int val2 = (((insn >> 1) & (7 << 0))); + switch (val2) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1938,8 +1938,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 23 : { - unsigned int val = (((insn >> 1) & (7 << 0))); - switch (val) + unsigned int val2 = (((insn >> 1) & (7 << 0))); + switch (val2) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1954,8 +1954,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 25 : { - unsigned int val = (((insn >> 1) & (7 << 0))); - switch (val) + unsigned int val2 = (((insn >> 1) & (7 << 0))); + switch (val2) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1970,8 +1970,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 27 : { - unsigned int val = (((insn >> 1) & (7 << 0))); - switch (val) + unsigned int val2 = (((insn >> 1) & (7 << 0))); + switch (val2) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1986,8 +1986,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 29 : { - unsigned int val = (((insn >> 1) & (7 << 0))); - switch (val) + unsigned int val2 = (((insn >> 1) & (7 << 0))); + switch (val2) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -2002,8 +2002,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 31 : { - unsigned int val = (((insn >> 1) & (7 << 0))); - switch (val) + unsigned int val2 = (((insn >> 1) & (7 << 0))); + switch (val2) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -2021,8 +2021,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 228 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -2045,8 +2045,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 229 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -2069,8 +2069,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 230 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -2093,8 +2093,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 232 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -2117,8 +2117,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 233 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -2141,8 +2141,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 234 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -2165,8 +2165,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 236 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -2189,8 +2189,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 237 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -2213,8 +2213,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 238 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -2237,8 +2237,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 240 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -2261,8 +2261,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 241 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -2285,8 +2285,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 242 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -2309,8 +2309,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 244 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -2333,8 +2333,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 245 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -2357,8 +2357,8 @@ crisv10f_decode (SIM_CPU *current_cpu, IADDR pc, } case 246 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ diff --git a/sim/cris/decodev32.c b/sim/cris/decodev32.c index e9d453d5e4b6..9928f208cc63 100644 --- a/sim/cris/decodev32.c +++ b/sim/cris/decodev32.c @@ -332,8 +332,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, CGEN_INSN_WORD insn = base_insn; { - unsigned int val = (((insn >> 4) & (255 << 0))); - switch (val) + unsigned int val0 = (((insn >> 4) & (255 << 0))); + switch (val0) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -352,8 +352,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, case 14 : /* fall through */ case 15 : { - unsigned int val = (((insn >> 12) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 12) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -507,8 +507,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, case 146 : itype = CRISV32F_INSN_MULU_D; goto extract_sfmt_muls_b; case 147 : { - unsigned int val = (((insn >> 12) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 12) & (15 << 0))); + switch (val1) { case 2 : if ((base_insn & 0xffff) == 0x2930) @@ -558,8 +558,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, case 170 : itype = CRISV32F_INSN_SUB_M_D_M; goto extract_sfmt_add_m_d_m; case 171 : { - unsigned int val = (((insn >> 12) & (1 << 0))); - switch (val) + unsigned int val1 = (((insn >> 12) & (1 << 0))); + switch (val1) { case 0 : if ((base_insn & 0xfff0) == 0xab0) @@ -610,8 +610,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, case 255 : itype = CRISV32F_INSN_MOVEM_R_M_V32; goto extract_sfmt_movem_r_m_v32; case 192 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -634,8 +634,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 193 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -658,8 +658,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 194 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -682,8 +682,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 195 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -706,8 +706,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 196 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -730,8 +730,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 197 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -754,8 +754,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 198 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -778,8 +778,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 199 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -802,8 +802,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 200 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -826,8 +826,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 201 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -850,8 +850,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 202 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -874,8 +874,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 203 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -898,8 +898,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 204 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -922,8 +922,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 205 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -946,8 +946,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 206 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -970,8 +970,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 207 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -997,8 +997,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, case 210 : itype = CRISV32F_INSN_MULS_D; goto extract_sfmt_muls_b; case 211 : { - unsigned int val = (((insn >> 12) & (1 << 0))); - switch (val) + unsigned int val1 = (((insn >> 12) & (1 << 0))); + switch (val1) { case 0 : if ((base_insn & 0xfff0) == 0xd30) @@ -1013,8 +1013,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 212 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1037,8 +1037,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 213 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1061,8 +1061,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 214 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1089,8 +1089,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; case 218 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1129,8 +1129,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; case 223 : { - unsigned int val = (((insn >> 12) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 12) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1159,8 +1159,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 224 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1183,8 +1183,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 225 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1207,8 +1207,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 226 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1231,8 +1231,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 227 : { - unsigned int val = (((insn >> 12) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 12) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1240,8 +1240,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, case 8 : itype = CRISV32F_INSN_MOVE_M_SPRV32; goto extract_sfmt_move_m_sprv32; case 2 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val2 = (((insn >> 0) & (15 << 0))); + switch (val2) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1264,8 +1264,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 3 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val2 = (((insn >> 0) & (15 << 0))); + switch (val2) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1288,8 +1288,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 5 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val2 = (((insn >> 0) & (15 << 0))); + switch (val2) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1312,8 +1312,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 6 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val2 = (((insn >> 0) & (15 << 0))); + switch (val2) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1336,8 +1336,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 7 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val2 = (((insn >> 0) & (15 << 0))); + switch (val2) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1360,8 +1360,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 9 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val2 = (((insn >> 0) & (15 << 0))); + switch (val2) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1384,8 +1384,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 10 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val2 = (((insn >> 0) & (15 << 0))); + switch (val2) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1408,8 +1408,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 11 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val2 = (((insn >> 0) & (15 << 0))); + switch (val2) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1432,8 +1432,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 12 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val2 = (((insn >> 0) & (15 << 0))); + switch (val2) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1456,8 +1456,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 13 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val2 = (((insn >> 0) & (15 << 0))); + switch (val2) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1480,8 +1480,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 14 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val2 = (((insn >> 0) & (15 << 0))); + switch (val2) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1504,8 +1504,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 15 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val2 = (((insn >> 0) & (15 << 0))); + switch (val2) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1531,8 +1531,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 228 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1555,8 +1555,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 229 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1579,8 +1579,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 230 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1603,8 +1603,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 232 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1627,8 +1627,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 233 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1651,8 +1651,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 234 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1679,8 +1679,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; case 236 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1703,8 +1703,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 237 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1727,8 +1727,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 238 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1755,8 +1755,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; case 240 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1779,8 +1779,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 241 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1803,8 +1803,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 242 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1831,8 +1831,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty; case 244 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1855,8 +1855,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 245 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -1879,8 +1879,8 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc, } case 246 : { - unsigned int val = (((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : /* fall through */ case 1 : /* fall through */ diff --git a/sim/frv/decode.c b/sim/frv/decode.c index 876dda24c209..c3fee6faf673 100644 --- a/sim/frv/decode.c +++ b/sim/frv/decode.c @@ -868,13 +868,13 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, CGEN_INSN_WORD insn = base_insn; { - unsigned int val = (((insn >> 18) & (127 << 0))); - switch (val) + unsigned int val0 = (((insn >> 18) & (127 << 0))); + switch (val0) { case 0 : { - unsigned int val = (((insn >> 6) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (15 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0x1fc0fc0) == 0x0) @@ -921,8 +921,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 1 : { - unsigned int val = (((insn >> 6) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (15 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0x1fc0fc0) == 0x40000) @@ -971,8 +971,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 2 : { - unsigned int val = (((insn >> 6) & (63 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (63 << 0))); + switch (val1) { case 0 : itype = FRVBF_INSN_LDSB; goto extract_sfmt_ldsb; case 1 : itype = FRVBF_INSN_LDUB; goto extract_sfmt_ldsb; @@ -1033,8 +1033,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 3 : { - unsigned int val = (((insn >> 6) & (63 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (63 << 0))); + switch (val1) { case 0 : itype = FRVBF_INSN_STB; goto extract_sfmt_stb; case 1 : itype = FRVBF_INSN_STH; goto extract_sfmt_stb; @@ -1164,8 +1164,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 4 : { - unsigned int val = (((insn >> 25) & (15 << 2)) | ((insn >> 6) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 25) & (15 << 2)) | ((insn >> 6) & (3 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0x7fffffff) == 0x100000) @@ -1312,8 +1312,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; case 6 : { - unsigned int val = (((insn >> 27) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 27) & (15 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0x7ffcffff) == 0x180000) @@ -1342,8 +1342,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 7 : { - unsigned int val = (((insn >> 27) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 27) & (15 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0x7ffcffff) == 0x1c0000) @@ -1372,8 +1372,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 8 : { - unsigned int val = (((insn >> 27) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 27) & (15 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0x79ffffff) == 0x200000) @@ -1444,8 +1444,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 9 : { - unsigned int val = (((insn >> 27) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 27) & (15 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0x79fffffc) == 0x240000) @@ -1516,8 +1516,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 10 : { - unsigned int val = (((insn >> 6) & (31 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (31 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0x1ffffff) == 0x280000) @@ -1600,8 +1600,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; case 12 : { - unsigned int val = (((insn >> 25) & (1 << 0))); - switch (val) + unsigned int val1 = (((insn >> 25) & (1 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0x7ffc0fc0) == 0x300000) @@ -1616,8 +1616,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 13 : { - unsigned int val = (((insn >> 25) & (1 << 0))); - switch (val) + unsigned int val1 = (((insn >> 25) & (1 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0x7ffc0000) == 0x340000) @@ -1632,8 +1632,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 14 : { - unsigned int val = (((insn >> 25) & (15 << 2)) | ((insn >> 14) & (1 << 1)) | ((insn >> 13) & (1 << 0))); - switch (val) + unsigned int val1 = (((insn >> 25) & (15 << 2)) | ((insn >> 14) & (1 << 1)) | ((insn >> 13) & (1 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0x7ffcffff) == 0x384000) @@ -1641,8 +1641,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; case 1 : { - unsigned int val = (((insn >> 14) & (1 << 0))); - switch (val) + unsigned int val2 = (((insn >> 14) & (1 << 0))); + switch (val2) { case 0 : if ((entire_insn & 0x7ffcefff) == 0x382000) @@ -1921,8 +1921,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, case 27 : itype = FRVBF_INSN_UMULICC; goto extract_sfmt_smulicc; case 28 : { - unsigned int val = (((insn >> 27) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 27) & (15 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0x7fffffff) == 0x700000) @@ -1951,8 +1951,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 29 : { - unsigned int val = (((insn >> 27) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 27) & (15 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0x7fffffff) == 0x740000) @@ -2031,8 +2031,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, case 69 : itype = FRVBF_INSN_NLDDI; goto extract_sfmt_nlddi; case 70 : { - unsigned int val = (((insn >> 6) & (7 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (7 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0x1fc0fc0) == 0x1180000) @@ -2084,8 +2084,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, case 87 : itype = FRVBF_INSN_STQFI; goto extract_sfmt_ldqfi; case 88 : { - unsigned int val = (((insn >> 6) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (3 << 0))); + switch (val1) { case 0 : itype = FRVBF_INSN_CADD; goto extract_sfmt_cadd; case 1 : itype = FRVBF_INSN_CSUB; goto extract_sfmt_cadd; @@ -2096,8 +2096,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 89 : { - unsigned int val = (((insn >> 6) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (3 << 0))); + switch (val1) { case 0 : itype = FRVBF_INSN_CADDCC; goto extract_sfmt_caddcc; case 1 : itype = FRVBF_INSN_CSUBCC; goto extract_sfmt_caddcc; @@ -2108,8 +2108,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 90 : { - unsigned int val = (((insn >> 6) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (3 << 0))); + switch (val1) { case 0 : itype = FRVBF_INSN_CAND; goto extract_sfmt_cadd; case 1 : itype = FRVBF_INSN_COR; goto extract_sfmt_cadd; @@ -2123,8 +2123,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 91 : { - unsigned int val = (((insn >> 6) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (3 << 0))); + switch (val1) { case 0 : itype = FRVBF_INSN_CANDCC; goto extract_sfmt_caddcc; case 1 : itype = FRVBF_INSN_CORCC; goto extract_sfmt_caddcc; @@ -2134,8 +2134,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 92 : { - unsigned int val = (((insn >> 6) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (3 << 0))); + switch (val1) { case 0 : itype = FRVBF_INSN_CSLL; goto extract_sfmt_cadd; case 1 : itype = FRVBF_INSN_CSRL; goto extract_sfmt_cadd; @@ -2145,8 +2145,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 93 : { - unsigned int val = (((insn >> 6) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (3 << 0))); + switch (val1) { case 0 : itype = FRVBF_INSN_CSLLCC; goto extract_sfmt_caddcc; case 1 : itype = FRVBF_INSN_CSRLCC; goto extract_sfmt_caddcc; @@ -2156,8 +2156,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 94 : { - unsigned int val = (((insn >> 6) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (3 << 0))); + switch (val1) { case 0 : itype = FRVBF_INSN_CLDSB; goto extract_sfmt_cldsb; case 1 : itype = FRVBF_INSN_CLDUB; goto extract_sfmt_cldsb; @@ -2168,8 +2168,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 95 : { - unsigned int val = (((insn >> 6) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (3 << 0))); + switch (val1) { case 0 : itype = FRVBF_INSN_CLD; goto extract_sfmt_cldsb; case 1 : itype = FRVBF_INSN_CLDD; goto extract_sfmt_cldd; @@ -2179,8 +2179,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 96 : { - unsigned int val = (((insn >> 6) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (3 << 0))); + switch (val1) { case 0 : itype = FRVBF_INSN_CLDBF; goto extract_sfmt_cldbf; case 1 : itype = FRVBF_INSN_CLDHF; goto extract_sfmt_cldbf; @@ -2191,8 +2191,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 97 : { - unsigned int val = (((insn >> 6) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (3 << 0))); + switch (val1) { case 0 : itype = FRVBF_INSN_CLDSBU; goto extract_sfmt_cldsbu; case 1 : itype = FRVBF_INSN_CLDUBU; goto extract_sfmt_cldsbu; @@ -2203,8 +2203,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 98 : { - unsigned int val = (((insn >> 6) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (3 << 0))); + switch (val1) { case 0 : itype = FRVBF_INSN_CLDU; goto extract_sfmt_cldsbu; case 1 : itype = FRVBF_INSN_CLDDU; goto extract_sfmt_clddu; @@ -2214,8 +2214,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 99 : { - unsigned int val = (((insn >> 6) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (3 << 0))); + switch (val1) { case 0 : itype = FRVBF_INSN_CLDBFU; goto extract_sfmt_cldbfu; case 1 : itype = FRVBF_INSN_CLDHFU; goto extract_sfmt_cldbfu; @@ -2226,8 +2226,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 100 : { - unsigned int val = (((insn >> 6) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (3 << 0))); + switch (val1) { case 0 : itype = FRVBF_INSN_CSTB; goto extract_sfmt_cstb; case 1 : itype = FRVBF_INSN_CSTH; goto extract_sfmt_cstb; @@ -2238,8 +2238,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 101 : { - unsigned int val = (((insn >> 6) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (3 << 0))); + switch (val1) { case 0 : itype = FRVBF_INSN_CSTQ; goto extract_sfmt_cldq; case 2 : itype = FRVBF_INSN_CSWAP; goto extract_sfmt_cswap; @@ -2249,8 +2249,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 102 : { - unsigned int val = (((insn >> 6) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (3 << 0))); + switch (val1) { case 0 : itype = FRVBF_INSN_CSTBF; goto extract_sfmt_cstbf; case 1 : itype = FRVBF_INSN_CSTHF; goto extract_sfmt_cstbf; @@ -2261,8 +2261,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 103 : { - unsigned int val = (((insn >> 6) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (3 << 0))); + switch (val1) { case 0 : itype = FRVBF_INSN_CSTBU; goto extract_sfmt_cstbu; case 1 : itype = FRVBF_INSN_CSTHU; goto extract_sfmt_cstbu; @@ -2273,8 +2273,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 104 : { - unsigned int val = (((insn >> 6) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (3 << 0))); + switch (val1) { case 0 : itype = FRVBF_INSN_CSTBFU; goto extract_sfmt_cstbfu; case 1 : itype = FRVBF_INSN_CSTHFU; goto extract_sfmt_cstbfu; @@ -2285,8 +2285,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 105 : { - unsigned int val = (((insn >> 6) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (3 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0x1fff0c0) == 0x1a40000) @@ -2309,13 +2309,13 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 106 : { - unsigned int val = (((insn >> 26) & (15 << 1)) | ((insn >> 6) & (1 << 0))); - switch (val) + unsigned int val1 = (((insn >> 26) & (15 << 1)) | ((insn >> 6) & (1 << 0))); + switch (val1) { case 0 : { - unsigned int val = (((insn >> 24) & (1 << 1)) | ((insn >> 7) & (1 << 0))); - switch (val) + unsigned int val2 = (((insn >> 24) & (1 << 1)) | ((insn >> 7) & (1 << 0))); + switch (val2) { case 0 : /* fall through */ case 2 : @@ -2462,8 +2462,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 107 : { - unsigned int val = (((insn >> 6) & (1 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (1 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0x1fff0c0) == 0x1ac0000) @@ -2478,8 +2478,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 108 : { - unsigned int val = (((insn >> 6) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (3 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0x1fff0c0) == 0x1b00000) @@ -2498,8 +2498,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 109 : { - unsigned int val = (((insn >> 6) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (3 << 0))); + switch (val1) { case 0 : itype = FRVBF_INSN_CFADDS; goto extract_sfmt_cfadds; case 1 : itype = FRVBF_INSN_CFSUBS; goto extract_sfmt_cfadds; @@ -2512,8 +2512,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 110 : { - unsigned int val = (((insn >> 6) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (3 << 0))); + switch (val1) { case 0 : itype = FRVBF_INSN_CFMULS; goto extract_sfmt_cfadds; case 1 : itype = FRVBF_INSN_CFDIVS; goto extract_sfmt_cfadds; @@ -2526,8 +2526,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 111 : { - unsigned int val = (((insn >> 6) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (3 << 0))); + switch (val1) { case 0 : itype = FRVBF_INSN_CFMADDS; goto extract_sfmt_cfmadds; case 1 : itype = FRVBF_INSN_CFMSUBS; goto extract_sfmt_cfmadds; @@ -2538,8 +2538,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 112 : { - unsigned int val = (((insn >> 6) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (3 << 0))); + switch (val1) { case 0 : itype = FRVBF_INSN_CMAND; goto extract_sfmt_cmand; case 1 : itype = FRVBF_INSN_CMOR; goto extract_sfmt_cmand; @@ -2553,8 +2553,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 113 : { - unsigned int val = (((insn >> 6) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (3 << 0))); + switch (val1) { case 0 : itype = FRVBF_INSN_CMADDHSS; goto extract_sfmt_cmaddhss; case 1 : itype = FRVBF_INSN_CMADDHUS; goto extract_sfmt_cmaddhss; @@ -2565,8 +2565,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 114 : { - unsigned int val = (((insn >> 6) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (3 << 0))); + switch (val1) { case 0 : itype = FRVBF_INSN_CMMULHS; goto extract_sfmt_cmmulhs; case 1 : itype = FRVBF_INSN_CMMULHU; goto extract_sfmt_cmmulhs; @@ -2577,8 +2577,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 115 : { - unsigned int val = (((insn >> 6) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (3 << 0))); + switch (val1) { case 0 : itype = FRVBF_INSN_CMQADDHSS; goto extract_sfmt_cmqaddhss; case 1 : itype = FRVBF_INSN_CMQADDHUS; goto extract_sfmt_cmqaddhss; @@ -2589,8 +2589,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 116 : { - unsigned int val = (((insn >> 6) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (3 << 0))); + switch (val1) { case 0 : itype = FRVBF_INSN_CMQMULHS; goto extract_sfmt_cmqmulhs; case 1 : itype = FRVBF_INSN_CMQMULHU; goto extract_sfmt_cmqmulhs; @@ -2601,8 +2601,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 117 : { - unsigned int val = (((insn >> 6) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (3 << 0))); + switch (val1) { case 0 : itype = FRVBF_INSN_CMCPXRS; goto extract_sfmt_cmcpxrs; case 1 : itype = FRVBF_INSN_CMCPXRU; goto extract_sfmt_cmcpxrs; @@ -2613,8 +2613,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 118 : { - unsigned int val = (((insn >> 6) & (1 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (1 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0x1fc00c0) == 0x1d80080) @@ -2629,8 +2629,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 119 : { - unsigned int val = (((insn >> 6) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (3 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0x1fff0c0) == 0x1dc0000) @@ -2649,8 +2649,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 120 : { - unsigned int val = (((insn >> 6) & (63 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (63 << 0))); + switch (val1) { case 0 : itype = FRVBF_INSN_MQXMACHS; goto extract_sfmt_mqmachs; case 1 : itype = FRVBF_INSN_MQXMACXHS; goto extract_sfmt_mqmachs; @@ -2712,13 +2712,13 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 121 : { - unsigned int val = (((insn >> 7) & (1 << 3)) | ((insn >> 6) & (7 << 0))); - switch (val) + unsigned int val1 = (((insn >> 7) & (1 << 3)) | ((insn >> 6) & (7 << 0))); + switch (val1) { case 0 : { - unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); - switch (val) + unsigned int val2 = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); + switch (val2) { case 0 : if ((entire_insn & 0x1ffffc0) == 0x1e40000) @@ -2735,8 +2735,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 1 : { - unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); - switch (val) + unsigned int val2 = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); + switch (val2) { case 0 : if ((entire_insn & 0x1ffffc0) == 0x1e40040) @@ -2753,8 +2753,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 2 : { - unsigned int val = (((insn >> 9) & (1 << 0))); - switch (val) + unsigned int val2 = (((insn >> 9) & (1 << 0))); + switch (val2) { case 0 : if ((entire_insn & 0x1ffffc0) == 0x1e40080) @@ -2769,8 +2769,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 3 : { - unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); - switch (val) + unsigned int val2 = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); + switch (val2) { case 0 : if ((entire_insn & 0x1ffffc0) == 0x1e400c0) @@ -2783,8 +2783,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 4 : { - unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); - switch (val) + unsigned int val2 = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); + switch (val2) { case 0 : if ((entire_insn & 0x1ffffc0) == 0x1e40100) @@ -2797,8 +2797,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 5 : { - unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); - switch (val) + unsigned int val2 = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); + switch (val2) { case 0 : if ((entire_insn & 0x1ffffc0) == 0x1e40140) @@ -2817,8 +2817,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 6 : { - unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); - switch (val) + unsigned int val2 = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); + switch (val2) { case 0 : itype = FRVBF_INSN_FADDS; goto extract_sfmt_fadds; case 1 : itype = FRVBF_INSN_FMAS; goto extract_sfmt_fmas; @@ -2829,8 +2829,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 7 : { - unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); - switch (val) + unsigned int val2 = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); + switch (val2) { case 0 : itype = FRVBF_INSN_FSUBS; goto extract_sfmt_fadds; case 1 : itype = FRVBF_INSN_FMSS; goto extract_sfmt_fmas; @@ -2841,8 +2841,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 8 : { - unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); - switch (val) + unsigned int val2 = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); + switch (val2) { case 0 : if ((entire_insn & 0x1ffffc0) == 0x1e40400) @@ -2859,8 +2859,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 9 : { - unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); - switch (val) + unsigned int val2 = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); + switch (val2) { case 0 : if ((entire_insn & 0x1ffffc0) == 0x1e40440) @@ -2877,8 +2877,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 10 : { - unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); - switch (val) + unsigned int val2 = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); + switch (val2) { case 0 : if ((entire_insn & 0x1ffffc0) == 0x1e40480) @@ -2897,8 +2897,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 11 : { - unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); - switch (val) + unsigned int val2 = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); + switch (val2) { case 0 : if ((entire_insn & 0x1ffffc0) == 0x1e404c0) @@ -2911,8 +2911,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 12 : { - unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); - switch (val) + unsigned int val2 = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); + switch (val2) { case 0 : if ((entire_insn & 0x1ffffc0) == 0x1e40500) @@ -2925,8 +2925,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 13 : { - unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); - switch (val) + unsigned int val2 = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); + switch (val2) { case 0 : if ((entire_insn & 0x1ffffc0) == 0x1e40540) @@ -2943,8 +2943,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 14 : { - unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); - switch (val) + unsigned int val2 = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); + switch (val2) { case 0 : itype = FRVBF_INSN_FDADDS; goto extract_sfmt_fmas; case 1 : itype = FRVBF_INSN_FDSADS; goto extract_sfmt_fmas; @@ -2955,8 +2955,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 15 : { - unsigned int val = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); - switch (val) + unsigned int val2 = (((insn >> 10) & (1 << 1)) | ((insn >> 9) & (1 << 0))); + switch (val2) { case 0 : itype = FRVBF_INSN_FDSUBS; goto extract_sfmt_fmas; case 1 : itype = FRVBF_INSN_FDMULCS; goto extract_sfmt_fmas; @@ -2970,8 +2970,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 122 : { - unsigned int val = (((insn >> 6) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (15 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0x1ffffc0) == 0x1e80000) @@ -3038,8 +3038,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 123 : { - unsigned int val = (((insn >> 6) & (63 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (63 << 0))); + switch (val1) { case 0 : itype = FRVBF_INSN_MAND; goto extract_sfmt_mand; case 1 : itype = FRVBF_INSN_MOR; goto extract_sfmt_mand; @@ -3126,8 +3126,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; case 59 : { - unsigned int val = (((insn >> 17) & (1 << 0))); - switch (val) + unsigned int val2 = (((insn >> 17) & (1 << 0))); + switch (val2) { case 0 : if ((entire_insn & 0x1ffffff) == 0x1ec0ec0) @@ -3135,8 +3135,8 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; case 1 : { - unsigned int val = (((insn >> 25) & (63 << 0))); - switch (val) + unsigned int val3 = (((insn >> 25) & (63 << 0))); + switch (val3) { case 0 : /* fall through */ case 1 : /* fall through */ diff --git a/sim/iq2000/decode.c b/sim/iq2000/decode.c index c9b891528134..48ca2fd347cf 100644 --- a/sim/iq2000/decode.c +++ b/sim/iq2000/decode.c @@ -269,13 +269,13 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, CGEN_INSN_WORD insn = base_insn; { - unsigned int val = (((insn >> 26) & (63 << 0))); - switch (val) + unsigned int val0 = (((insn >> 26) & (63 << 0))); + switch (val0) { case 0 : { - unsigned int val = (((insn >> 1) & (1 << 4)) | ((insn >> 0) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 1) & (1 << 4)) | ((insn >> 0) & (15 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xffe0003f) == 0x0) @@ -386,8 +386,8 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, } case 1 : { - unsigned int val = (((insn >> 17) & (1 << 3)) | ((insn >> 16) & (7 << 0))); - switch (val) + unsigned int val1 = (((insn >> 17) & (1 << 3)) | ((insn >> 16) & (7 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xfc1f0000) == 0x4000000) @@ -459,8 +459,8 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty; case 16 : { - unsigned int val = (((insn >> 19) & (15 << 3)) | ((insn >> 15) & (3 << 1)) | ((insn >> 4) & (1 << 0))); - switch (val) + unsigned int val1 = (((insn >> 19) & (15 << 3)) | ((insn >> 15) & (3 << 1)) | ((insn >> 4) & (1 << 0))); + switch (val1) { case 0 : /* fall through */ case 2 : /* fall through */ @@ -519,8 +519,8 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, } case 17 : { - unsigned int val = (((insn >> 22) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 22) & (3 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xffe007ff) == 0x44000000) @@ -543,13 +543,13 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, } case 18 : { - unsigned int val = (((insn >> 16) & (3 << 5)) | ((insn >> 0) & (31 << 0))); - switch (val) + unsigned int val1 = (((insn >> 16) & (3 << 5)) | ((insn >> 0) & (31 << 0))); + switch (val1) { case 0 : { - unsigned int val = (((insn >> 23) & (1 << 0))); - switch (val) + unsigned int val2 = (((insn >> 23) & (1 << 0))); + switch (val2) { case 0 : if ((entire_insn & 0xffe007ff) == 0x48000000) @@ -636,8 +636,8 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty; case 64 : { - unsigned int val = (((insn >> 23) & (1 << 0))); - switch (val) + unsigned int val2 = (((insn >> 23) & (1 << 0))); + switch (val2) { case 0 : if ((entire_insn & 0xffe007ff) == 0x48400000) @@ -655,8 +655,8 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, } case 19 : { - unsigned int val = (((insn >> 19) & (31 << 2)) | ((insn >> 0) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 19) & (31 << 2)) | ((insn >> 0) & (3 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xffe007ff) == 0x4c000000) @@ -664,8 +664,8 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty; case 4 : { - unsigned int val = (((insn >> 2) & (3 << 0))); - switch (val) + unsigned int val2 = (((insn >> 2) & (3 << 0))); + switch (val2) { case 0 : if ((entire_insn & 0xffe007ff) == 0x4c200000) @@ -684,8 +684,8 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, } case 5 : { - unsigned int val = (((insn >> 3) & (1 << 0))); - switch (val) + unsigned int val2 = (((insn >> 3) & (1 << 0))); + switch (val2) { case 0 : if ((entire_insn & 0xffe007ff) == 0x4c200001) @@ -700,8 +700,8 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, } case 6 : { - unsigned int val = (((insn >> 2) & (3 << 0))); - switch (val) + unsigned int val2 = (((insn >> 2) & (3 << 0))); + switch (val2) { case 0 : if ((entire_insn & 0xffe007ff) == 0x4c200002) @@ -720,8 +720,8 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, } case 7 : { - unsigned int val = (((insn >> 2) & (1 << 0))); - switch (val) + unsigned int val2 = (((insn >> 2) & (1 << 0))); + switch (val2) { case 0 : if ((entire_insn & 0xffe007ff) == 0x4c200003) @@ -751,8 +751,8 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc, case 34 : /* fall through */ case 35 : { - unsigned int val = (((insn >> 16) & (3 << 0))); - switch (val) + unsigned int val2 = (((insn >> 16) & (3 << 0))); + switch (val2) { case 0 : if ((entire_insn & 0xffff0000) == 0x4d000000) diff --git a/sim/lm32/decode.c b/sim/lm32/decode.c index 826fd5866848..2bfbf13aac5e 100644 --- a/sim/lm32/decode.c +++ b/sim/lm32/decode.c @@ -187,8 +187,8 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc, CGEN_INSN_WORD insn = base_insn; { - unsigned int val = (((insn >> 26) & (63 << 0))); - switch (val) + unsigned int val0 = (((insn >> 26) & (63 << 0))); + switch (val0) { case 0 : itype = LM32BF_INSN_SRUI; goto extract_sfmt_addi; case 1 : itype = LM32BF_INSN_NORI; goto extract_sfmt_andi; @@ -260,8 +260,8 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc, itype = LM32BF_INSN_X_INVALID; goto extract_sfmt_empty; case 43 : { - unsigned int val = (((insn >> 1) & (1 << 1)) | ((insn >> 0) & (1 << 0))); - switch (val) + unsigned int val1 = (((insn >> 1) & (1 << 1)) | ((insn >> 0) & (1 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xffffffff) == 0xac000002) diff --git a/sim/m32r/decode.c b/sim/m32r/decode.c index 7d802a3fa074..dae456d1af03 100644 --- a/sim/m32r/decode.c +++ b/sim/m32r/decode.c @@ -229,8 +229,8 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, CGEN_INSN_WORD insn = base_insn; { - unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0))); - switch (val) + unsigned int val0 = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0))); + switch (val0) { case 0 : itype = M32RBF_INSN_SUBV; goto extract_sfmt_addv; case 1 : itype = M32RBF_INSN_SUBX; goto extract_sfmt_addx; @@ -258,8 +258,8 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, case 26 : itype = M32RBF_INSN_MVTC; goto extract_sfmt_mvtc; case 28 : { - unsigned int val = (((insn >> 8) & (1 << 0))); - switch (val) + unsigned int val1 = (((insn >> 8) & (1 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xfff0) == 0x1ec0) @@ -325,8 +325,8 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, case 85 : itype = M32RBF_INSN_SLLI; goto extract_sfmt_slli; case 87 : { - unsigned int val = (((insn >> 0) & (1 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (1 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xf0ff) == 0x5070) @@ -349,8 +349,8 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty; case 95 : { - unsigned int val = (((insn >> 0) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (3 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xf0ff) == 0x50f0) @@ -385,8 +385,8 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, case 111 : itype = M32RBF_INSN_LDI8; goto extract_sfmt_ldi8; case 112 : { - unsigned int val = (((insn >> 8) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 8) & (15 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xffff) == 0x7000) @@ -417,8 +417,8 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, case 126 : /* fall through */ case 127 : { - unsigned int val = (((insn >> 8) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 8) & (15 << 0))); + switch (val1) { case 1 : itype = M32RBF_INSN_SETPSW; goto extract_sfmt_setpsw; case 2 : itype = M32RBF_INSN_CLRPSW; goto extract_sfmt_clrpsw; @@ -544,8 +544,8 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc, case 254 : /* fall through */ case 255 : { - unsigned int val = (((insn >> 8) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 8) & (3 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xff000000) == 0xfc000000) diff --git a/sim/m32r/decode2.c b/sim/m32r/decode2.c index 60909af1887e..c8677e663a37 100644 --- a/sim/m32r/decode2.c +++ b/sim/m32r/decode2.c @@ -272,8 +272,8 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, CGEN_INSN_WORD insn = base_insn; { - unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0))); - switch (val) + unsigned int val0 = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0))); + switch (val0) { case 0 : itype = M32R2F_INSN_SUBV; goto extract_sfmt_addv; case 1 : itype = M32R2F_INSN_SUBX; goto extract_sfmt_addx; @@ -284,8 +284,8 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, case 6 : itype = M32R2F_INSN_CMPEQ; goto extract_sfmt_cmp; case 7 : { - unsigned int val = (((insn >> 8) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 8) & (3 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xfff0) == 0x70) @@ -318,8 +318,8 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, case 26 : itype = M32R2F_INSN_MVTC; goto extract_sfmt_mvtc; case 28 : { - unsigned int val = (((insn >> 8) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 8) & (3 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xfff0) == 0x1cc0) @@ -403,8 +403,8 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, case 85 : itype = M32R2F_INSN_SLLI; goto extract_sfmt_slli; case 87 : { - unsigned int val = (((insn >> 0) & (1 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (1 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xf0f3) == 0x5070) @@ -435,8 +435,8 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; case 95 : { - unsigned int val = (((insn >> 0) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (3 << 0))); + switch (val1) { case 0 : itype = M32R2F_INSN_MVFACHI_A; goto extract_sfmt_mvfachi_a; case 1 : itype = M32R2F_INSN_MVFACLO_A; goto extract_sfmt_mvfachi_a; @@ -462,8 +462,8 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, case 111 : itype = M32R2F_INSN_LDI8; goto extract_sfmt_ldi8; case 112 : { - unsigned int val = (((insn >> 7) & (15 << 1)) | ((insn >> 0) & (1 << 0))); - switch (val) + unsigned int val1 = (((insn >> 7) & (15 << 1)) | ((insn >> 0) & (1 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xffff) == 0x7000) @@ -512,8 +512,8 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, case 126 : /* fall through */ case 127 : { - unsigned int val = (((insn >> 8) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 8) & (15 << 0))); + switch (val1) { case 1 : itype = M32R2F_INSN_SETPSW; goto extract_sfmt_setpsw; case 2 : itype = M32R2F_INSN_CLRPSW; goto extract_sfmt_clrpsw; @@ -536,8 +536,8 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty; case 134 : { - unsigned int val = (((entire_insn >> 8) & (3 << 0))); - switch (val) + unsigned int val1 = (((entire_insn >> 8) & (3 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xf0f0ffff) == 0x80600000) @@ -561,8 +561,8 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, case 142 : itype = M32R2F_INSN_OR3; goto extract_sfmt_or3; case 144 : { - unsigned int val = (((entire_insn >> 3) & (3 << 0))); - switch (val) + unsigned int val1 = (((entire_insn >> 3) & (3 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xf0f0ffff) == 0x90000000) @@ -581,8 +581,8 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, } case 145 : { - unsigned int val = (((entire_insn >> 3) & (3 << 0))); - switch (val) + unsigned int val1 = (((entire_insn >> 3) & (3 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xf0f0ffff) == 0x90100000) @@ -601,8 +601,8 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, } case 146 : { - unsigned int val = (((entire_insn >> 3) & (3 << 0))); - switch (val) + unsigned int val1 = (((entire_insn >> 3) & (3 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xf0f0ffff) == 0x90200000) @@ -621,8 +621,8 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, } case 147 : { - unsigned int val = (((entire_insn >> 3) & (3 << 0))); - switch (val) + unsigned int val1 = (((entire_insn >> 3) & (3 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xf0f0ffff) == 0x90300000) @@ -725,8 +725,8 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc, case 254 : /* fall through */ case 255 : { - unsigned int val = (((insn >> 8) & (7 << 0))); - switch (val) + unsigned int val1 = (((insn >> 8) & (7 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xff000000) == 0xf8000000) diff --git a/sim/m32r/decodex.c b/sim/m32r/decodex.c index ad2c3f01dac3..864ea82128e2 100644 --- a/sim/m32r/decodex.c +++ b/sim/m32r/decodex.c @@ -265,8 +265,8 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, CGEN_INSN_WORD insn = base_insn; { - unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0))); - switch (val) + unsigned int val0 = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0))); + switch (val0) { case 0 : itype = M32RXF_INSN_SUBV; goto extract_sfmt_addv; case 1 : itype = M32RXF_INSN_SUBX; goto extract_sfmt_addx; @@ -277,8 +277,8 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, case 6 : itype = M32RXF_INSN_CMPEQ; goto extract_sfmt_cmp; case 7 : { - unsigned int val = (((insn >> 8) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 8) & (3 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xfff0) == 0x70) @@ -311,8 +311,8 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, case 26 : itype = M32RXF_INSN_MVTC; goto extract_sfmt_mvtc; case 28 : { - unsigned int val = (((insn >> 8) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 8) & (3 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xfff0) == 0x1cc0) @@ -396,8 +396,8 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, case 85 : itype = M32RXF_INSN_SLLI; goto extract_sfmt_slli; case 87 : { - unsigned int val = (((insn >> 0) & (1 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (1 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xf0f3) == 0x5070) @@ -428,8 +428,8 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; case 95 : { - unsigned int val = (((insn >> 0) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 0) & (3 << 0))); + switch (val1) { case 0 : itype = M32RXF_INSN_MVFACHI_A; goto extract_sfmt_mvfachi_a; case 1 : itype = M32RXF_INSN_MVFACLO_A; goto extract_sfmt_mvfachi_a; @@ -455,8 +455,8 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, case 111 : itype = M32RXF_INSN_LDI8; goto extract_sfmt_ldi8; case 112 : { - unsigned int val = (((insn >> 7) & (15 << 1)) | ((insn >> 0) & (1 << 0))); - switch (val) + unsigned int val1 = (((insn >> 7) & (15 << 1)) | ((insn >> 0) & (1 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xffff) == 0x7000) @@ -505,8 +505,8 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, case 126 : /* fall through */ case 127 : { - unsigned int val = (((insn >> 8) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 8) & (15 << 0))); + switch (val1) { case 1 : itype = M32RXF_INSN_SETPSW; goto extract_sfmt_setpsw; case 2 : itype = M32RXF_INSN_CLRPSW; goto extract_sfmt_clrpsw; @@ -529,8 +529,8 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty; case 134 : { - unsigned int val = (((entire_insn >> 8) & (3 << 0))); - switch (val) + unsigned int val1 = (((entire_insn >> 8) & (3 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xf0f0ffff) == 0x80600000) @@ -554,8 +554,8 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, case 142 : itype = M32RXF_INSN_OR3; goto extract_sfmt_or3; case 144 : { - unsigned int val = (((entire_insn >> 4) & (1 << 0))); - switch (val) + unsigned int val1 = (((entire_insn >> 4) & (1 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xf0f0ffff) == 0x90000000) @@ -666,8 +666,8 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, case 254 : /* fall through */ case 255 : { - unsigned int val = (((insn >> 8) & (7 << 0))); - switch (val) + unsigned int val1 = (((insn >> 8) & (7 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xff000000) == 0xf8000000) diff --git a/sim/or1k/decode.c b/sim/or1k/decode.c index c04afe5cb313..aab70108245a 100644 --- a/sim/or1k/decode.c +++ b/sim/or1k/decode.c @@ -266,8 +266,8 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, CGEN_INSN_WORD insn = base_insn; { - unsigned int val = (((insn >> 21) & (63 << 5)) | ((insn >> 0) & (31 << 0))); - switch (val) + unsigned int val0 = (((insn >> 21) & (63 << 5)) | ((insn >> 0) & (31 << 0))); + switch (val0) { case 0 : /* fall through */ case 1 : /* fall through */ @@ -466,8 +466,8 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty; case 192 : { - unsigned int val = (((insn >> 16) & (1 << 0))); - switch (val) + unsigned int val1 = (((insn >> 16) & (1 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xfc1f0000) == 0x18000000) @@ -516,8 +516,8 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty; case 256 : { - unsigned int val = (((insn >> 23) & (7 << 0))); - switch (val) + unsigned int val1 = (((insn >> 23) & (7 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xffff0000) == 0x20000000) @@ -574,8 +574,8 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, case 286 : /* fall through */ case 287 : { - unsigned int val = (((insn >> 24) & (1 << 0))); - switch (val) + unsigned int val1 = (((insn >> 24) & (1 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xffff0000) == 0x20000000) @@ -1132,8 +1132,8 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, case 1502 : /* fall through */ case 1503 : { - unsigned int val = (((insn >> 6) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (3 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xfc00ffc0) == 0xb8000000) @@ -1187,8 +1187,8 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, case 1534 : /* fall through */ case 1535 : { - unsigned int val = (((insn >> 21) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 21) & (15 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xffe00000) == 0xbc000000) @@ -1283,8 +1283,8 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty; case 1600 : { - unsigned int val = (((insn >> 5) & (7 << 0))); - switch (val) + unsigned int val1 = (((insn >> 5) & (7 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xfc0007ff) == 0xc8000000) @@ -1327,8 +1327,8 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty; case 1608 : { - unsigned int val = (((insn >> 5) & (1 << 0))); - switch (val) + unsigned int val1 = (((insn >> 5) & (1 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xffe007ff) == 0xc8000008) @@ -1343,8 +1343,8 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, } case 1609 : { - unsigned int val = (((insn >> 5) & (1 << 0))); - switch (val) + unsigned int val1 = (((insn >> 5) & (1 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xffe007ff) == 0xc8000009) @@ -1359,8 +1359,8 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, } case 1610 : { - unsigned int val = (((insn >> 5) & (1 << 0))); - switch (val) + unsigned int val1 = (((insn >> 5) & (1 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xffe007ff) == 0xc800000a) @@ -1375,8 +1375,8 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, } case 1611 : { - unsigned int val = (((insn >> 5) & (1 << 0))); - switch (val) + unsigned int val1 = (((insn >> 5) & (1 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xffe007ff) == 0xc800000b) @@ -1391,8 +1391,8 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, } case 1612 : { - unsigned int val = (((insn >> 5) & (1 << 0))); - switch (val) + unsigned int val1 = (((insn >> 5) & (1 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xffe007ff) == 0xc800000c) @@ -1407,8 +1407,8 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, } case 1613 : { - unsigned int val = (((insn >> 5) & (1 << 0))); - switch (val) + unsigned int val1 = (((insn >> 5) & (1 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xffe007ff) == 0xc800000d) @@ -1427,8 +1427,8 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty; case 1616 : { - unsigned int val = (((insn >> 6) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (3 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xfc0000ff) == 0xc8000010) @@ -1471,8 +1471,8 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty; case 1624 : { - unsigned int val = (((insn >> 5) & (1 << 0))); - switch (val) + unsigned int val1 = (((insn >> 5) & (1 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xffe004ff) == 0xc8000018) @@ -1487,8 +1487,8 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, } case 1625 : { - unsigned int val = (((insn >> 5) & (1 << 0))); - switch (val) + unsigned int val1 = (((insn >> 5) & (1 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xffe004ff) == 0xc8000019) @@ -1503,8 +1503,8 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, } case 1626 : { - unsigned int val = (((insn >> 5) & (1 << 0))); - switch (val) + unsigned int val1 = (((insn >> 5) & (1 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xffe004ff) == 0xc800001a) @@ -1519,8 +1519,8 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, } case 1627 : { - unsigned int val = (((insn >> 5) & (1 << 0))); - switch (val) + unsigned int val1 = (((insn >> 5) & (1 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xffe004ff) == 0xc800001b) @@ -1535,8 +1535,8 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, } case 1628 : { - unsigned int val = (((insn >> 5) & (1 << 0))); - switch (val) + unsigned int val1 = (((insn >> 5) & (1 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xffe004ff) == 0xc800001c) @@ -1551,8 +1551,8 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, } case 1629 : { - unsigned int val = (((insn >> 5) & (1 << 0))); - switch (val) + unsigned int val1 = (((insn >> 5) & (1 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xffe004ff) == 0xc800001d) @@ -1731,8 +1731,8 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty; case 1800 : { - unsigned int val = (((insn >> 6) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (3 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xfc0007ff) == 0xe0000008) @@ -1767,8 +1767,8 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty; case 1804 : { - unsigned int val = (((insn >> 6) & (3 << 0))); - switch (val) + unsigned int val1 = (((insn >> 6) & (3 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xfc00ffff) == 0xe000000c) @@ -1791,8 +1791,8 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, } case 1805 : { - unsigned int val = (((insn >> 7) & (3 << 1)) | ((insn >> 6) & (1 << 0))); - switch (val) + unsigned int val1 = (((insn >> 7) & (3 << 1)) | ((insn >> 6) & (1 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xfc00ffff) == 0xe000000d) @@ -1815,8 +1815,8 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty; case 1807 : { - unsigned int val = (((insn >> 8) & (1 << 0))); - switch (val) + unsigned int val1 = (((insn >> 8) & (1 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xfc0007ff) == 0xe000000f) @@ -1831,8 +1831,8 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc, } case 1824 : { - unsigned int val = (((insn >> 21) & (15 << 0))); - switch (val) + unsigned int val1 = (((insn >> 21) & (15 << 0))); + switch (val1) { case 0 : if ((entire_insn & 0xffe007ff) == 0xe4000000)