From patchwork Fri Dec 22 01:23:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Frysinger X-Patchwork-Id: 82715 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A0B673858410 for ; Fri, 22 Dec 2023 01:24:19 +0000 (GMT) X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from smtp.gentoo.org (woodpecker.gentoo.org [140.211.166.183]) by sourceware.org (Postfix) with ESMTP id 3CEDB3858C2D for ; Fri, 22 Dec 2023 01:24:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3CEDB3858C2D Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gentoo.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gentoo.org ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 3CEDB3858C2D Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=140.211.166.183 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703208241; cv=none; b=Xq14pT99nLMia01BGXE/DBJTARj84JFoG6y9Eg4JRy7ez5hIAarrRTgdis3MWHg4Bl0i6rKkmkH/zEZs4YNRr45KSGLAo4PC4UnFEIugUcCXMELvJs5U/4rTINqBBVMzSjQT/9WP0RGXy7qndtI1Q2fzUBb2yyInyA3Be7rG4m4= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703208241; c=relaxed/simple; bh=ow59Qffz0bsVKLpws699l3nV2RHeh4TGE95/Cqyc5rQ=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=KWGYbRP630UwL0p4GG3bVwXuuCmxYh/Kc6DOQunMsz4SnJOaG7QiYe+lq+75vt2yIJAjnaC4GhUnmJd7ggFQqLyP0HdX19tUZvO3VMJCTsOt2utGwcX6CZrjdeginlREiMAzZQq5V4McpBZSkbiZg4SQino3Ac6VjFgqR60OVhU= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by smtp.gentoo.org (Postfix, from userid 559) id C840B340943; Fri, 22 Dec 2023 01:23:59 +0000 (UTC) From: Mike Frysinger To: gdb-patches@sourceware.org Subject: [PATCH 02/15] sim: arm: fix -Wshadow=local warnings Date: Thu, 21 Dec 2023 20:23:42 -0500 Message-ID: <20231222012355.7504-2-vapier@gentoo.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231222012355.7504-1-vapier@gentoo.org> References: <20231222012355.7504-1-vapier@gentoo.org> MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_DMARC_STATUS, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org Remove duplicate nested variable declarations, rename some to avoid confusion when the type is different or the original value should be retained, and fix some weirdness with nested enums in structs. --- sim/arm/armemu.c | 38 +++++++++++++++++--------------------- sim/arm/thumbemu.c | 22 ++++++---------------- sim/arm/wrapper.c | 16 +++++++--------- 3 files changed, 30 insertions(+), 46 deletions(-) diff --git a/sim/arm/armemu.c b/sim/arm/armemu.c index 2b8ae007cb56..cafaabbf637c 100644 --- a/sim/arm/armemu.c +++ b/sim/arm/armemu.c @@ -1023,7 +1023,7 @@ handle_v6_insn (ARMul_State * state, ARMword instr) Rn = BITS (0, 3); if (Rn != 0xF) { - ARMword val = state->Reg[Rn] & ~(-(1 << ((msb + 1) - lsb))); + val = state->Reg[Rn] & ~(-(1 << ((msb + 1) - lsb))); state->Reg[Rd] |= val << lsb; } return 1; @@ -1434,8 +1434,6 @@ ARMul_Emulate26 (ARMul_State * state) { if (BITS (25, 27) == 5) /* BLX(1) */ { - ARMword dest; - state->Reg[14] = pc + 4; /* Force entry into Thumb mode. */ @@ -1568,10 +1566,10 @@ check_PMUintr: if (do_int && (cp14r0 & ARMul_CP14_R0_INTEN2)) { - ARMword temp; + ARMword cp; - if (state->CPRead[13] (state, 8, & temp) - && (temp & ARMul_CP13_R8_PMUS)) + if (state->CPRead[13] (state, 8, & cp) + && (cp & ARMul_CP13_R8_PMUS)) ARMul_Abort (state, ARMul_FIQV); else ARMul_Abort (state, ARMul_IRQV); @@ -1604,8 +1602,8 @@ check_PMUintr: if (BITS (4, 7) == 0xD) { /* XScale Load Consecutive insn. */ - ARMword temp = GetLS7RHS (state, instr); - ARMword temp2 = BIT (23) ? LHS + temp : LHS - temp; + ARMword temp1 = GetLS7RHS (state, instr); + ARMword temp2 = BIT (23) ? LHS + temp1 : LHS - temp1; ARMword addr = BIT (24) ? temp2 : LHS; if (BIT (12)) @@ -1630,8 +1628,8 @@ check_PMUintr: else if (BITS (4, 7) == 0xF) { /* XScale Store Consecutive insn. */ - ARMword temp = GetLS7RHS (state, instr); - ARMword temp2 = BIT (23) ? LHS + temp : LHS - temp; + ARMword temp1 = GetLS7RHS (state, instr); + ARMword temp2 = BIT (23) ? LHS + temp1 : LHS - temp1; ARMword addr = BIT (24) ? temp2 : LHS; if (BIT (12)) @@ -2313,15 +2311,13 @@ check_PMUintr: if (BITS (4, 7) == 3) { /* BLX(2) */ - ARMword temp; - if (TFLAG) - temp = (pc + 2) | 1; + dest = (pc + 2) | 1; else - temp = pc + 4; + dest = pc + 4; WriteR15Branch (state, state->Reg[RHSReg]); - state->Reg[14] = temp; + state->Reg[14] = dest; break; } } @@ -2487,7 +2483,7 @@ check_PMUintr: /* ElSegundo SMLALxy insn. */ ARMdword op1 = state->Reg[BITS (0, 3)]; ARMdword op2 = state->Reg[BITS (8, 11)]; - ARMdword dest; + ARMdword result; if (BIT (5)) op1 >>= 16; @@ -2500,11 +2496,11 @@ check_PMUintr: if (op2 & 0x8000) op2 -= 65536; - dest = (ARMdword) state->Reg[BITS (16, 19)] << 32; - dest |= state->Reg[BITS (12, 15)]; - dest += op1 * op2; - state->Reg[BITS (12, 15)] = dest; - state->Reg[BITS (16, 19)] = dest >> 32; + result = (ARMdword) state->Reg[BITS (16, 19)] << 32; + result |= state->Reg[BITS (12, 15)]; + result += op1 * op2; + state->Reg[BITS (12, 15)] = result; + state->Reg[BITS (16, 19)] = result >> 32; break; } diff --git a/sim/arm/thumbemu.c b/sim/arm/thumbemu.c index 99f51ef34691..58a9c85ce2b9 100644 --- a/sim/arm/thumbemu.c +++ b/sim/arm/thumbemu.c @@ -2131,14 +2131,11 @@ ARMul_ThumbDecode (ARMul_State * state, if ((tinstr & (1 << 10)) == 0) { /* Format 4 */ - struct - { + struct insn_format { ARMword opcode; - enum - { t_norm, t_shift, t_neg, t_mul } - otype; - } - subset[16] = + enum { t_norm, t_shift, t_neg, t_mul } otype; + }; + struct insn_format subset[16] = { { 0xE0100000, t_norm}, /* ANDS Rd,Rd,Rs */ { 0xE0300000, t_norm}, /* EORS Rd,Rd,Rs */ @@ -2161,14 +2158,7 @@ ARMul_ThumbDecode (ARMul_State * state, if (in_IT_block ()) { - struct - { - ARMword opcode; - enum - { t_norm, t_shift, t_neg, t_mul } - otype; - } - subset[16] = + struct insn_format it_subset[16] = { { 0xE0000000, t_norm}, /* AND Rd,Rd,Rs */ { 0xE0200000, t_norm}, /* EOR Rd,Rd,Rs */ @@ -2187,7 +2177,7 @@ ARMul_ThumbDecode (ARMul_State * state, { 0xE1C00000, t_norm}, /* BIC Rd,Rd,Rs */ { 0xE1E00000, t_norm} /* MVN Rd,Rs */ }; - *ainstr = subset[(tinstr & 0x03C0) >> 6].opcode; /* base */ + *ainstr = it_subset[(tinstr & 0x03C0) >> 6].opcode; /* base */ } switch (subset[(tinstr & 0x03C0) >> 6].otype) diff --git a/sim/arm/wrapper.c b/sim/arm/wrapper.c index 8d928a6f79f9..06512754725b 100644 --- a/sim/arm/wrapper.c +++ b/sim/arm/wrapper.c @@ -746,14 +746,14 @@ sim_target_parse_command_line (int argc, char ** argv) while (* ptr) { - int i; + int o; - for (i = ARRAY_SIZE (options); i--;) - if (strncmp (ptr, options[i].swi_option, - strlen (options[i].swi_option)) == 0) + for (o = ARRAY_SIZE (options); o--;) + if (strncmp (ptr, options[o].swi_option, + strlen (options[o].swi_option)) == 0) { - swi_mask |= options[i].swi_mask; - ptr += strlen (options[i].swi_option); + swi_mask |= options[o].swi_mask; + ptr += strlen (options[o].swi_option); if (* ptr == ',') ++ ptr; @@ -761,7 +761,7 @@ sim_target_parse_command_line (int argc, char ** argv) break; } - if (i < 0) + if (o < 0) break; } @@ -884,8 +884,6 @@ sim_open (SIM_OPEN_KIND kind, if (argv_copy[1] != NULL) { - int i; - /* Scan for memory-size switches. */ for (i = 0; (argv_copy[i] != NULL) && (argv_copy[i][0] != 0); i++) if (argv_copy[i][0] == '-' && argv_copy[i][1] == 'm')