diff mbox series

[v4,1/2,sim/riscv] Fix crash during instruction decoding

Message ID 20231221111139.26341-2-jaydeep.patil@imgtec.com
State New
Headers
Series sim: riscv: Compressed instruction simulation |

Checks

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Commit Message

Jaydeep Patil Dec. 21, 2023, 11:11 a.m. UTC 
  From: Jaydeep Patil <jaydeep.patil@imgtec.com>

The match_never() function has been removed and thus step_once() crashes
during instruction decoding. Fixed it by checking for null pointer before
invoking function attached to match_func member of riscv_opcode structure.
---
 opcodes/riscv-dis.c  | 2 +-
 sim/riscv/sim-main.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

Comments

Mike Frysinger Dec. 21, 2023, 12:48 p.m. UTC | #1 
sim looks fine
-mike
diff mbox series

Patch

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 68674380797..a89ebdd32ac 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -818,7 +818,7 @@  riscv_disassemble_insn (bfd_vma memaddr,
 	  if (op->pinfo == INSN_MACRO)
 	    continue;
 	  /* Does the opcode match?  */
-	  if (! (op->match_func) (op, word))
+	  if (! op->match_func || ! (op->match_func) (op, word))
 	    continue;
 	  /* Is this a pseudo-instruction and may we print it as such?  */
 	  if (no_aliases && (op->pinfo & INSN_ALIAS))
diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index afdfcf50656..8a23d2aa1f9 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -1041,7 +1041,7 @@  void step_once (SIM_CPU *cpu)
   for (; op->name; op++)
     {
       /* Does the opcode match?  */
-      if (! op->match_func (op, iw))
+      if (! op->match_func || ! op->match_func (op, iw))
 	continue;
       /* Is this a pseudo-instruction and may we print it as such?  */
       if (op->pinfo & INSN_ALIAS)