From patchwork Thu Dec 21 07:01:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Frysinger X-Patchwork-Id: 82640 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5EC4C3865C1D for ; Thu, 21 Dec 2023 07:01:56 +0000 (GMT) X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from smtp.gentoo.org (dev.gentoo.org [IPv6:2001:470:ea4a:1:5054:ff:fec7:86e4]) by sourceware.org (Postfix) with ESMTP id D71F7385E456 for ; Thu, 21 Dec 2023 07:01:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D71F7385E456 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gentoo.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gentoo.org ARC-Filter: OpenARC Filter v1.0.0 sourceware.org D71F7385E456 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2001:470:ea4a:1:5054:ff:fec7:86e4 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703142097; cv=none; b=Sv7I8r9RMbeOsqkMSkxnfZfbxkRZ2FaDj+je0GuMvUlbqPUq5RMVgyV24r3aVsBCfs0NQRmClCP/Qx5dqyfBbX4vPzsy74jE35+BdORl/q4gHwFw6XEs4cLH7DZfCGqJ1c9ZMG4ErHPeuTv3lcZErhtOP0nXMeVnU3lR9mMQiyM= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703142097; c=relaxed/simple; bh=30W8Ev903GRpF9gytTwzeGHe3VEEXbXI86kShfWkWi8=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=HTKLhuNabVk7cSyc2KMVmibXljNFNPbAnEDWDjAjyCR9f4ol77spnuRAyVfaUxn6m1F6E8Gn7TnW9NUWtU6feta5F/GZaozz5tfHeh8M6E9CEz8wGYNXUteWXrMlJ/CsMjnYc+u20312Z1+729HQ9wbAZdW7OmNmCgbDRhcZSo0= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by smtp.gentoo.org (Postfix, from userid 559) id 59288340943; Thu, 21 Dec 2023 07:01:35 +0000 (UTC) From: Mike Frysinger To: gdb-patches@sourceware.org Subject: [PATCH/committed 04/20] sim: aarch64: fix -Wimplicit-fallthrough warnings Date: Thu, 21 Dec 2023 02:01:11 -0500 Message-ID: <20231221070127.19142-4-vapier@gentoo.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231221070127.19142-1-vapier@gentoo.org> References: <20231221070127.19142-1-vapier@gentoo.org> MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org Replace some fall through comments with the attribute, and add some default abort calls when the compiler can't figure out that the set of values were already fully enumerated in the switch statement. --- sim/aarch64/simulator.c | 40 ++++++++++++++++++++++++++-------------- 1 file changed, 26 insertions(+), 14 deletions(-) diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c index 3dba1b7f0dc7..8825819a3910 100644 --- a/sim/aarch64/simulator.c +++ b/sim/aarch64/simulator.c @@ -129,11 +129,11 @@ expand_logical_immediate (uint32_t S, uint32_t R, uint32_t N) /* Replicate the value according to SIMD size. */ switch (simd_size) { - case 2: imm = (imm << 2) | imm; - case 4: imm = (imm << 4) | imm; - case 8: imm = (imm << 8) | imm; - case 16: imm = (imm << 16) | imm; - case 32: imm = (imm << 32) | imm; + case 2: imm = (imm << 2) | imm; ATTRIBUTE_FALLTHROUGH; + case 4: imm = (imm << 4) | imm; ATTRIBUTE_FALLTHROUGH; + case 8: imm = (imm << 8) | imm; ATTRIBUTE_FALLTHROUGH; + case 16: imm = (imm << 16) | imm; ATTRIBUTE_FALLTHROUGH; + case 32: imm = (imm << 32) | imm; ATTRIBUTE_FALLTHROUGH; case 64: break; default: return 0; } @@ -2040,12 +2040,12 @@ extreg32 (sim_cpu *cpu, unsigned int lo, Extension extension) { case UXTB: return aarch64_get_reg_u8 (cpu, lo, NO_SP); case UXTH: return aarch64_get_reg_u16 (cpu, lo, NO_SP); - case UXTW: /* Fall through. */ + case UXTW: ATTRIBUTE_FALLTHROUGH; case UXTX: return aarch64_get_reg_u32 (cpu, lo, NO_SP); case SXTB: return aarch64_get_reg_s8 (cpu, lo, NO_SP); case SXTH: return aarch64_get_reg_s16 (cpu, lo, NO_SP); - case SXTW: /* Fall through. */ - case SXTX: /* Fall through. */ + case SXTW: ATTRIBUTE_FALLTHROUGH; + case SXTX: ATTRIBUTE_FALLTHROUGH; default: return aarch64_get_reg_s32 (cpu, lo, NO_SP); } } @@ -3346,7 +3346,7 @@ do_vec_MOV_immediate (sim_cpu *cpu) case 0xa: /* 16-bit, shift by 8. */ val <<= 8; - /* Fall through. */ + ATTRIBUTE_FALLTHROUGH; case 0x8: /* 16-bit, no shift. */ for (i = 0; i < (full ? 8 : 4); i++) aarch64_set_vec_u16 (cpu, vd, i, val); @@ -3355,7 +3355,7 @@ do_vec_MOV_immediate (sim_cpu *cpu) case 0xd: /* 32-bit, mask shift by 16. */ val <<= 8; val |= 0xFF; - /* Fall through. */ + ATTRIBUTE_FALLTHROUGH; case 0xc: /* 32-bit, mask shift by 8. */ val <<= 8; val |= 0xFF; @@ -3416,6 +3416,7 @@ do_vec_MVNI (sim_cpu *cpu) case 0xa: /* 16-bit, 8 bit shift. */ val <<= 8; + ATTRIBUTE_FALLTHROUGH; case 0x8: /* 16-bit, no shift. */ val = ~ val; for (i = 0; i < (full ? 8 : 4); i++) @@ -3425,6 +3426,7 @@ do_vec_MVNI (sim_cpu *cpu) case 0xd: /* 32-bit, mask shift by 16. */ val <<= 8; val |= 0xFF; + ATTRIBUTE_FALLTHROUGH; case 0xc: /* 32-bit, mask shift by 8. */ val <<= 8; val |= 0xFF; @@ -4691,6 +4693,8 @@ do_vec_SCVTF (sim_cpu *cpu) aarch64_get_vec_##SOURCE##64 (cpu, vm, i) \ ? -1ULL : 0); \ return; \ + default: \ + HALT_UNALLOC; \ } \ } \ while (0) @@ -4726,6 +4730,8 @@ do_vec_SCVTF (sim_cpu *cpu) aarch64_get_vec_##SOURCE##64 (cpu, vn, i) \ CMP 0 ? -1ULL : 0); \ return; \ + default: \ + HALT_UNALLOC; \ } \ } \ while (0) @@ -5316,6 +5322,7 @@ do_vec_sub_long (sim_cpu *cpu) { case 2: /* SSUBL2. */ bias = 2; + ATTRIBUTE_FALLTHROUGH; case 0: /* SSUBL. */ switch (size) { @@ -5349,6 +5356,7 @@ do_vec_sub_long (sim_cpu *cpu) case 3: /* USUBL2. */ bias = 2; + ATTRIBUTE_FALLTHROUGH; case 1: /* USUBL. */ switch (size) { @@ -5811,6 +5819,7 @@ do_vec_xtl (sim_cpu *cpu) { case 2: /* SXTL2, SSHLL2. */ bias = 2; + ATTRIBUTE_FALLTHROUGH; case 0: /* SXTL, SSHLL. */ if (INSTR (21, 21)) { @@ -5851,6 +5860,7 @@ do_vec_xtl (sim_cpu *cpu) case 3: /* UXTL2, USHLL2. */ bias = 2; + ATTRIBUTE_FALLTHROUGH; case 1: /* UXTL, USHLL. */ if (INSTR (21, 21)) { @@ -8568,6 +8578,7 @@ dexSimpleFPIntegerConvert (sim_cpu *cpu) case 1: scvtd32 (cpu); return; case 2: scvtf (cpu); return; case 3: scvtd (cpu); return; + default: HALT_UNALLOC; } case 6: /* FMOV GR, Vec. */ @@ -8593,6 +8604,7 @@ dexSimpleFPIntegerConvert (sim_cpu *cpu) case 1: fcvtszd32 (cpu); return; case 2: fcvtszs (cpu); return; case 3: fcvtszd (cpu); return; + default: HALT_UNALLOC; } case 25: do_fcvtzu (cpu); return; @@ -9186,7 +9198,7 @@ do_scalar_FCM (sim_cpu *cpu) case 3: /* 011 */ val1 = fabs (val1); val2 = fabs (val2); - /* Fall through. */ + ATTRIBUTE_FALLTHROUGH; case 2: /* 010 */ result = val1 >= val2; break; @@ -9194,7 +9206,7 @@ do_scalar_FCM (sim_cpu *cpu) case 7: /* 111 */ val1 = fabs (val1); val2 = fabs (val2); - /* Fall through. */ + ATTRIBUTE_FALLTHROUGH; case 6: /* 110 */ result = val1 > val2; break; @@ -9219,7 +9231,7 @@ do_scalar_FCM (sim_cpu *cpu) case 3: /* 011 */ val1 = fabsf (val1); val2 = fabsf (val2); - /* Fall through. */ + ATTRIBUTE_FALLTHROUGH; case 2: /* 010 */ result = val1 >= val2; break; @@ -9227,7 +9239,7 @@ do_scalar_FCM (sim_cpu *cpu) case 7: /* 111 */ val1 = fabsf (val1); val2 = fabsf (val2); - /* Fall through. */ + ATTRIBUTE_FALLTHROUGH; case 6: /* 110 */ result = val1 > val2; break;