[PATCH/committed] sim: rx: add missing break to memory write

Message ID 20231221064445.14761-1-vapier@gentoo.org
State New
Headers
Series [PATCH/committed] sim: rx: add missing break to memory write |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_gdb_build--master-aarch64 success Testing passed
linaro-tcwg-bot/tcwg_gdb_build--master-arm warning Patch is already merged
linaro-tcwg-bot/tcwg_gdb_check--master-aarch64 success Testing passed

Commit Message

Mike Frysinger Dec. 21, 2023, 6:44 a.m. UTC
  It doesn't seem like we want to keep executing the next block of code
after processing the request.
---
 sim/rx/mem.c | 1 +
 1 file changed, 1 insertion(+)
  

Patch

diff --git a/sim/rx/mem.c b/sim/rx/mem.c
index 2cba4cb3662d..83e23023f943 100644
--- a/sim/rx/mem.c
+++ b/sim/rx/mem.c
@@ -324,6 +324,7 @@  mem_put_byte (unsigned int address, unsigned char value)
 	  halt_pipeline_stats ();
 	else
 	  reset_pipeline_stats ();
+	break;
       }
 #endif